Two bits per transistor: Intel 8087

Intel developed the 8087 chip in 1980 in order to improve PC performance with 8086/8088 processor lines (such as the IBM PC) when performing floating point operations. Since the first microprocessors were designed to perform operations with integers, the execution of operations with floating-point numbers was slow, which already speak of performing transcendental operations, such as trigonometric functions or logarithms. The 8087 coprocessor significantly increased the speed of performing tasks with a floating point, everything was performed almost 100 times faster. The 8087 architecture was also implemented in later Intel processors, and the 8087 instructions are still used in modern x86 PCs. Intel introduced the 8087 chip in 198? designed to improve the performance of floating-point computing on the 8086 and 8088 processors. 3r3321.  3r33337.
 3r33337. Two bits per transistor: Intel 8087  3r33337. 3r311. 3r33333.
 3r33337. Since early microprocessors only worked with integers, floating-point arithmetic was slow, and transcendental operations, such as triggers or logarithms, looked even worse. Adding the math coprocessor 8087 to the system made it possible to speed up operations with a floating point 100 times. The 8087 architecture has become part of the later Intel processors, and the 8087 instructions (although outdated) are still part of modern x86 desktops.
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 3r33337. The 8087 chip provided fast floating point arithmetic for the original IBM PC and became part of the x86 architecture used today. One of the unusual features of the 8087 is a multi-level ROM (read only memory) capable of storing two bits per transistor, which is twice the density of a regular ROM. Instead of storing binary data, each cell in the 8087 ROM stored one of four different values, which were then decoded into two bits. Since 8087 needed a large amount of ROM for microcode (1), and the number of transistors on a chip was very limited, Intel used unusual technology to solve the problem. In this article, I will explain how Intel implemented this multi-level ROM.
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 3r33337. I opened the 8087 chip and photographed it with a microscope, taking a photo below. In the photo I indicated the main functional blocks, based on my own reverse engineering (Click to enlarge image). The processor matrix 8087 is quite complicated, with 4?000 transistors (2). 8087 uses 80-bit floating-point numbers: 64 bits are reserved for the mantissa, 15 bits for the exponent, and another sign bit. (An example of a number with base 10: in the number ??? × ??? is the mantissa, and 23 is the exponent). At the bottom of the photo, the word “fraction processing” marks a part of the scheme for the mantissa. From left to right, this includes: a constant store, a 64-bit offset, a 64-bit adder /subtractor, and a stack of registers. Slightly above is the circuit for handling exponents.
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 3r33337.  3r33337. Chip math coprocessor for floating point operations Intel 808? with the designation of the main functional blocks 3r3223.
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 3r33337. Executing the 8087 instruction took several steps, and in some cases more than 1000. The 8087 firmware used microcode to define low-level operations at each step: shifts, increment, memory samples, reading constants, etc. You can perceive the microcode as a simple program, written in the form of microinstructions, in which each microinstruction generates control signals for various components of the chip. In the photo above, you can see the ROM with the microcode program 8087. ROM occupies most of the chip, clearly showing why a compact multi-level ROM was necessary. To the left of the ROM is the “engine” on which the microcode program was run, in fact, a simple processor.
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 3r33337. 8087 worked as a coprocessor with an 8086 processor. When the 8086 detected a special floating point instruction, the processor ignored it and allowed the 8087 to execute the instruction in parallel. I will not explain in detail the internal work of 808? but, briefly, floating point operations were implemented using integer addition /subtraction and shift operations. To add or subtract two floating point numbers, 8087 performed a bitwise offset of the number until the binary delimiters (that is, the decimal separator is a comma, but in the binary system) match, and then add or subtract the mantissa. Multiplication, division and square root were performed by multiple shifts, additions or subtractions. Transcendental operations (tan, arctan, log, power) used CORDIC algorithms that use shifts and add special constants, processing one bit at a time. 8087 also encountered many particular cases: infinity, overflow, NaN (not a number), denormalized numbers and several rounding modes. The microcode stored in the ROM controlled all these operations.
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Implementation ROM 3r33253.
 3r33337. Chip 8087 consists of a tiny silicon matrix, on which silicon is doped with impurities in places in order to obtain the desired semiconductor properties. Polysilicon (a special type of silicon) that forms wires and transistors is deposited on a silicon surface. And finally, the metal layer on top of the silicone completes the working electrical circuit. In the photo below, on the left side, a small part of the chip is shown, as it is visible under the microscope, showing yellowish metallic wiring. On the right side of the photo, the metal was removed with acid, exposing polysilicon and silicon. When polysilicon crosses silicon, a transistor is formed. The pink areas are doped silicon, and the thin vertical lines are polysilicon. Small circles are the contacts between the silicon and metal layers connecting them together.
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 3r33337.  3r33337. [i] ROM structure in an Intel 8087 FPU. The metal layer is shown on the left, and polysilicon and silicon on the right are 3r3323223.
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 3r33337. Although there are many ways to build ROMs, the standard way is to create a grid of "cells", where each cell stores one bit. Each cell can have a transistor (which means 0 bits) or not have a transistor, which means 1 bit. In the image above, you can see a grid of cells with transistors (where polysilicon is deposited on silicon) and missing transistors (where there are gaps in silicon). To read information from the ROM, one column selection line is activated (based on the address) to select the bits stored in this column and to receive one bit from each row at the output. You can see the vertical lines of column selection (column select lines) from polysilicon, and the horizontal metal rows in the photo above. Vertical doped silicon lines are grounded.
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 3r33337. The diagram below (corresponding to the 4 × 4 ROM segment) explains how the ROM functions. Each cell either has a transistor (black), or does not have a transistor (highlighted in gray). When voltage is applied to the column selection line of the polysilicon, the transistors in this column turn on and ground the corresponding metal rows. (in this case, the NMOS transistor is similar to a gate that is open if the input is ? and is closed if the input is 1.) The metal “rows” of the circuit output the data stored in the selected “column”.
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 3r33337.  3r33337. [i] Diagram of a 4x4 ROM segment

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 3r33337. The column selection signals are generated by the decoder circuit. Since this circuit is built from NOR valves, I will first explain the design of the valves. The diagram below shows a four-input NOR gate built from four transistors and a pull-up resistor (although in fact, a special transistor performs the function of a resistor). In the left part of the circuit, all inputs are ? therefore all transistors are disabled, and the pull-up resistor keeps the output signal at a high level. In the right side, one was fed to one of the inputs by turning on the transistor. The transistor is grounded, so the output signal is now "low" level. Thus, if any inputs are high (1), the output is low (0). So this circuit implements the NOR valve.
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 3r33337.  3r33337. 4-input NOR gate built from NMOS 3r-3223 transistors.
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 3r33337. The column selection decoder circuit accepts incoming address bits and activates the corresponding selection string. The decoder contains an 8-input NOR gate for each column, that is, one NOR gate for each address. The photo shows two NOR elements that generate column selection signals (for simplicity, I will show only four of the 8 inputs). Each column uses a different combination of address lines and augmented address lines as input, choosing a different address. Address lines are in the metal layer, which is removed in the photo below; address lines are highlighted in green. To determine the address associated with a column, look at the square contacts associated with each transistor and note which address lines are connected. If all address lines connected to the transistors of the column are at a low (0) level, the NOR gate will select this column.
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 3r33337. [i] Part of the address decoder. Address decoder selects odd columns in ROM, counting from right to left. The numbers at the top show the address associated with each exit

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 3r33337. The photo below shows a small part of the ROM decoder with all 8 inputs for NOR gates. You can read binary addresses by carefully examining the connections in the address bar. Note the binary pattern: connections a1 change values ​​in each column, connections a2 alternate every two columns, connections a3 every four columns, and so on. D. Connection a0 is fixed because this decoder scheme selects odd columns; A similar ROM scheme selects even-numbered addresses (such a separation was necessary for the decoder to fit on the chip, since each column of the decoder is twice as wide as the ROM cell).
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 3r33337. A part of the address decoder for the ROM 8087 microcode. The decoder converts the 8-bit address into the signals for selecting the column 3r-2323.
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 3r33337. The last component of the ROM is a set of multiplexers, which reduces the 64 output lines to 8 lines. Each 8-to-1 multiplexer selects one of its 8 inputs based on the address. The diagram below shows one of the 8087 processor row multiplexers, built with eight large pass-through transistors, each of which is connected to one of the “row” lines. All transistors are connected to the output so when the selected transistor is turned on, it transmits its input to the output. Multiplexer transistors are much, much larger than transistors in ROM to reduce ROM signal distortion. A decoder (similar to the one discussed earlier, but smaller) generates eight multiplexer control lines from three address lines.
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 3r33337.  3r33337. [i] One of 8-row multiplexers in ROM. Here you can see layers of (poly) silicon, with metallic compounds painted orange

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 3r33337. To summarize, the ROM stores the bits in the grid. It uses eight address bits to select a column in the grid. Then the three bits of the address select the desired eight outputs from the “strings”.
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Multi-level ROM


 3r33337. So far I have explained the typical ROM device that stores one bit per cell. So how could the 8087 store two bits per cell? If you look closely, the microcode ROM 8087 contains four different sizes of transistors - if we assume the absence of the transistor as one of the sizes (6). With four options for each transistor, one cell can encode two bits, roughly doubling the density (7). The current section explains how the four sizes of transistors generate four different currents, and how analog and digital IC circuits convert these currents to two bits.
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 3r33337. A micrograph of the microcode ROM 8087 shows four different transistor sizes. This allows the ROM to store two bits per cell 3r33223.
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 3r33337. The size of the transistor regulates the current through the transistor (8). An important geometric factor is the different width of silicon (pink), where it intersects with polysilicon (vertical lines), creating transistors with different gate widths. Since the gate width controls the current through the transistor, four transistor sizes generate four different currents: the largest transistor passes most of the current, and the current does not flow at all if there is no transistor.
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 3r33337. The ROM current is converted to bits in several steps. First, the pull-up resistor converts the current to voltage. The three comparators then compare the voltage with the reference voltage to generate digital signals, determining which voltage is higher /lower. Finally, logic gates convert the comparator's output signals to two output bits. This scheme is repeated eight times, generating a total of 16 bits on the output.
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 3r33337.  3r33337. [i] The circuit for reading two bits from the ROM cell 3r33223.
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 3r33337. The diagram above performs these conversion steps. As a result, one of the ROM transistors is selected by the “column” selection line and the multiplexer (discussed earlier), which generates one of the four currents. Then, the pull-up resistor (12) converts the current of the transistor to voltage, with the result that the voltage depends on the size of the selected transistor. Comparators compare this voltage with three reference voltages, and output 1 if the ROM voltage is higher than the reference voltage. Comparators and reference voltages require careful design, since ROM voltages may differ by as little as 200 mV.
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 3r33337. The reference voltages are in the middle between the expected values ​​of the voltage of the ROM, which allows for some voltage fluctuations. The “low” voltage of the ROM is lower than all the reference voltages, so all the comparators will output 0. The second voltage of the ROM is higher than Ref ? so the lower comparator outputs 1. With the third voltage ROM, the lower two comparators output ? and at the maximum the voltage of the ROM at the output of all three comparators 1. Thus, the three comparators produce four different output patterns, depending on the transistor ROM. The logic elements then convert the comparator output to two output bits (10).
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 3r33337. The design of the comparator is interesting because it is a bridge between the analog and digital worlds, producing 1 or 0 if the voltage of the ROM is higher or lower than the reference voltage. Each comparator contains a differential amplifier, which amplifies the difference between the voltage of the ROM and the reference voltage. The output of the differential amplifier drives a gate, which stabilizes the output and converts it into a logic level signal. The differential amplifier (below) is a standard analog circuit. The current source (symbol below) provides a constant current. If one of the transistors has a higher input voltage than the other, most of the current passes through that transistor. The voltage drop across the resistors will cause the corresponding output to be lower, and the other output to be higher.
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 3r33337. [i] Diagram showing the operation of the differential pair. Most of the current will pass through a transistor with a higher input voltage, with the result that the corresponding output signal will be lower. The double circle symbol at the bottom is the DC source I

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 3r33337. The photo below shows one of the comparators on the chip; metal layer on top, transistors under it. I will consider only the highlights of this complex scheme; See note 12 for details. Signal from ROM and multiplexer comes on the left. Pull-up circuit 12 converts current to voltage. Two large differential amplifier transistors compare the voltage of the ROM with the reference voltage (input from the top). The outputs from the differential amplifier go to the gate circuit (scattered over the photo); shutter output is in the lower right corner. The current source of the differential amplifier and pull-up resistors are made of depletion-mode transistors. Each output circuit uses three comparators, which gives a total of 24 comparators.
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 3r33337. One of the comparators in 8087. The chip contains 24 comparators for converting voltage levels from a multi-level ROM to binary data
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 3r33337. Each reference voltage is generated by a carefully sized transistor and a pull-up circuit. The voltage reference circuit is designed to be as similar as possible to the ROM signal circuit, so that any changes in chip production will affect both elements in the same way. The reference voltage and the ROM signal use the same load circuit. In addition, each reference voltage circuit includes a very large transistor, identical to the multiplexer transistor, although there is no multiplexing in the reference signal circuit — just to ensure “matching” of the circuits. The three voltage reference circuits are identical, except for the size of the reference transistor (9).
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 3r33337.  3r33337. A circuit that generates three reference voltages. The size of the reference transistors - between the size of the transistors ROM. The oxide layer was not completely removed from this part of the matrix, because of which color swirls appeared in the photo
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 3r33337. To assemble the entire puzzle, the photo below shows the location of the components of the microcode ROM on the chip (12). The main part of the circuit ROM is transistors that store data. The column decoder circuit is located above and below the ROM data. Half of the column decoders are at the top, and half are at the bottom, for better layout. The output circuit is on the right. Eight multiplexers reduce 64 lines to eight lines. Then eight lines enter the comparators, generating 16 bits at the output of the ROM on the right. The reference circuit above the comparators generates three reference voltages. At the bottom right, a small string decoder controls the multiplexers.
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 3r33337.  3r33337. [i] Microcode ROM from Intel 8087 FPU with the marking of the main components 3r322323.
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 3r33337. Although initially it may seem that the multi-level ROM will be two times smaller than the usual ROM, the effect is not so noticeable due to the additional comparators scheme, and because the transistors themselves are slightly larger, due to the need to use several sizes. Despite this, a multi-level ROM saved about 40% of the space that would have occupied the usual ROM.
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 3r33337. Now that I understand the structure of the ROM, I can simply (but tiringly) read the contents of the ROM, just by looking at the size of each transistor under a microscope. But, without knowing the set of microcode instructions, the contents of the ROM is useless.
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Conclusions


 3r33337. The 8087 floating-point math coprocessor used an unusual “two bits per cell” structure to place microcode on the chip. Intel reused the multi-level ROM structure in 1981 in the doomed iAPX system. ??? As far as I can tell, interest in multi-level cell ROMs reached its peak in the 1980s and then waned. Probably due to the fact that, according to Moore's law, it is much easier to increase the capacity of the ROM by reducing the standard cell than by designing non-standard ROMs that require special analog circuits built with high tolerances (14).
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 3r33337. Surprisingly, the multi-level concept has recently returned, but already on flash memory. Many flash devices store two or more bits per cell (13). Flash memory has even reached a remarkable 4 bits per cell (requiring 16 different voltage levels) in consumer products recently announced (QLC, quad-level cell). Thus, the little-known technologies of the 1980s can come back again decades later.
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 3r33337. I report my latest blog posts on Twitter, so subscribe to @kenshirriff to read future articles on 8087. I also have an RSS feed. Thanks to Jeff Epler for offering to explore the ROM 8087. 3r3-3321.  3r33337.
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Notes and references


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The 8087 processor contains 1648 microcode words (if I correctly counted), with 16 bits in each word, a total of 2?368 bits. The size of the ROM does not have to be a power of two, and Intel can build it with any desired size. 3r3302.  3r33337.
Sources provide conflicting values ​​for the number of transistors in 8087: Intel states that 4?000 transistors and Wikipedia claims that 4?000. The discrepancy may be due to different ways of counting transistors. In particular, since the number of transistors in ROM, PLA, or a similar structure depends on the data stored in it, sources often consider “potential” transistors, rather than the number of physical transistors. Other discrepancies may be related to whether pull-up transistors are taken into account and whether high-current drivers are considered to be several parallel or one large transistor. 3r3302.  3r33337.
The interaction between the 8086 processor and the 8087 floating-point coprocessor is quite complex; I will explain some of the highlights. A simplified view is that 8087 watches the 8086 command stream and executes any instructions that are 8087 instructions. The difficulty is that the 8086 has a command prefetch buffer, so the selected command does not mean executable. Thus, 8087 duplicates the 8086 prefetch buffer (or smaller 8088 prefetch buffer), so it knows what 8086 is doing. Another obstacle is the complex addressing modes used by the 808? which use registers inside the processor. 8087 cannot perform these addressing modes, since it does not have access to the 8086 registers. Instead, when the 8086 sees the 8087 instruction, it samples the memory at the specified address, and ignores the result. Meanwhile, 8087 captures the address from the bus so that it can use it if it needs an address. If the 8087 is missing, you can expect a malfunction, but this does not happen. Instead, for a system without 808? the linker rewrites 8087 instructions, replacing them with subprogram calls into the emulation library. 3r3302.  3r33337.
The reason why ROMs typically use multiplexers at the outputs of rows is that it is inefficient to create ROMs with a large number of columns and several output bits, since the decoder circuit will be larger than the ROM data. The solution is to change the form of the ROM to keep the same bits, but with more rows and fewer columns. For example, a ROM can have 8 times more rows and 1/8 columns, which allows using a 1/8 size decoder. In addition, a long, narrow ROM (for example, 1 K × 16) is inconvenient to place on the chip, since it is not suitable as a simple unit. However, the "snake" design can also be used. For example, Intel's earliest memory samples were shift registers; 1405 contained 512 bits in one long shift register. To install it on a chip, the shift register was put back and forth about 20 times by a “snake”. 3r3302.  3r33337.
Some IBM computers used an unusual storage technique for storing microcode: holes were punched in Mylar cards (just like in ordinary punched cards), and a computer detected capacitively (link) holes. Some computers, such as Xerox Alto, had some microcode in the RAM. This allowed programs to modify the microcode, creating new instructions for their specific purposes. Many modern processors have a writeable microcode, so patches can fix bugs in the microcode. 3r3302.  3r33337.
I did not notice the four transistor sizes in the microcode ROM until I saw a mention in the Hacker News commentary that the 8087 used two-bit per cell technology. I was skeptical, but after a closer examination of the chip, I realized that the comment was correct. 3r3302.  3r33337.
Several other approaches were used in the 1980s to store several bits per cell. Mostek and other companies used one of the most common: alloy transistors in ROM had different threshold voltages. Using four different threshold voltages, you can store two bits per cell. Compared to Intel's geometric approach, the threshold approach provided greater density (since all transistors could be of a minimum size), but required more layers and processing steps to create a multi-level implantation. This approach used a new (at that time) ion implantation technology to carefully adjust the doping levels of each transistor. The biggest effect of ion implantation on integrated circuits was its use to create depleting transistors (transistors with negative threshold voltage), which worked much better than pull-up resistors in logic elements. Ion implantation was also used in the Z-80 microprocessor to create some transistor “traps”, circuits that looked like ordinary transistors under a microscope, but received implants that made them non-functional. This served as copy protection, since the manufacturer who tried to produce clones of the Z-80 processor by copying the chip with a microscope eventually received a chip that did not work correctly in different ways, some of which were difficult to detect. 3r3302.  3r33337.
The current through the transistor is proportional to the ratio between the width and the length of the gate. (The length is the distance between the source and the drain.) ROM transistors (and all but the smallest reference transistor) maintain a constant length and change the width, so reducing the width reduces the current. For MOSFET equations, see Wikipedia 3r3302.  3r33337.
The gate of the smallest reference transistor is rather longer than narrow, due to the properties of MOS transistors. The problem is that the reference transistors must be sized between the sizes of the ROMs of the transistors. In particular, for Reference ? a transistor of a smaller size than the smallest transistor of the ROM is required. But the smallest ROM transistor is already as small as possible, following manufacturing techniques. Note: to solve this problem, the polysilicon that crosses the middle reference transistor is much thicker horizontally. Since the properties of a MOSFET are determined by the ratio of the width to the height of its gate, the expansion of polysilicon works as well as the compression of silicon in order to make the transistor operate with a lower current. 3r3302.  3r33337.
The ROM logic decodes the size of the transistor in bits as follows: No transistor = 0? small transistor = 0? middle transistor = 1? large transistor = 10. This bit ordering saves several elements in the decoding logic; Since the mapping from transistor to bits is arbitrary, it does not matter that the sequence is not in order. (See "Two Bits Per Cell ROM", Stark). 3r3302.  3r33337.
The Intel iAPX 43203 (1981) interface processor used a multi-level ROM that is very similar to the 8087 chip. For details, see “The interface processor for the Intel VLSI ??? bit computer,” J. Bayliss et al., IEEE J. Solid-State Circuits vol. SC-1? pp. 522-53? October 1981 The 43203 interface processor provided I /O support for the iAPX 432 processor. Intel launched the iAPX 432 project in 1975 to create a “micro-mainframe” that will be the revolutionary Intel processor for the 1980s s. When delays occurred in the iAPX 432 project, Intel released the 8086 processor as a temporary solution in 1978. Although the Intel 8086 was a huge success, leading to desktop PCs and modern x86 architecture, the iAPX 432 project failed in 1986. 3r3302.  3r33337.
The diagram below (from the Multiple-Valued ROM Output Circuits) contains detailed information on the ROM read scheme. Conceptually, the ROM uses a pull-up resistor to convert the transistor current into voltage. The circuit actually uses a three-transistor circuit (T? T? T5) as a pull-up. T4 and T5 are essentially an inverter, providing negative feedback through T? which makes the circuit less sensitive to disturbances (such as production deviations). The comparator consists of a simple differential amplifier (yellow) with T6 acting as a current source. The output of the differential amplifier is converted to a stable logic level signal using a gate (green). 3r3302.  3r33337.
Flash memory is divided into SLC (one single level cell - one bit per cell), MLC (multi level cell - two bits per cell), TLC (triple level cell - three bits per cell) and QLC (quad level cell - four bits per cell). Often, flash memory with a higher number of bits per cell is cheaper, but less reliable, and wears out more slowly and more quickly due to smaller signal differences. 3r3302.  3r33337.
The magazine “Electronics” published a short article “Four-State Cell Doubles ROM Bit Capacity” (pp. 3? October ? 1980), which describes the Intel methodology, but this article is unclear and misleading. Intel published a detailed article “Two bits per cell ROM” in COMPCON (pp. 209-21? February 1981). The external team attempted to reverse engineer the more detailed specifications of Intel's circuits in “Multiple-valued ROM output circuits” (Proc. 14th Int. Symp. Multivalue Logic, 1984). Two articles describing memory using this technology are “ A Survey of Multivalued Memories "(" IEEE Transactions on Computers ", February 198? pp. 99–106) and" 3r-3300. A review of multiple-valued memory technology
(IEEE Symposium on Multivalued Logic, 1998). 3r3302.  3r33337. 3r3304.
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