Chisel - (not quite) a new approach to the development of digital logic

Chisel - (not quite) a new approach to the development of digital logic
 
With the development of microelectronics, rtl designs have become more and more. The re-usability of the code on verilog delivers a lot of inconvenience, even with the use of generate, macros and chips system verilog. Chisel, however, makes it possible to apply the full power of object and functional programming to the development of rtl, which is quite a welcome step, which can fill the lungs of light developers ASIC and FPGA.
 
In this article, we will give a brief overview of the main functional and consider some use cases, and also talk about the shortcomings of this language. In the future, if the ...
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Designing the CPU (CPU Design) LMC

Designing the CPU (CPU Design) LMC
 
Part I
 
Part II
 
Part III
 
 
This is the full version of the previous article.
 
 
We design Little Man Computer in Verilog.
 
 
Article about LMC was on Habré.
 
 
Online simulator of this computer here .
 
 
Let's write the RAM module consisting of four (ADDR_WIDTH = 2) four-bit (DATA_WIDTH = 4) words. Data is loaded into RAM from data_in at adr when the clock signal clk arrives.
 
module R0 # (parameter ADDR_WIDTH = ? DATA_WIDTH = 4)
(
input clk, clock signal
input[ADDR_WIDTH-1:0]adr, address
input[DATA_WIDTH-1:0]data_in...[/DATA][/ADDR]
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FPP via FPL: Accelerate the loading of FPGA

FPP via FPL: Accelerate the loading of FPGAHello!
 
Recently there was a task - to accelerate the loading of FPGA. From the appearance of power to the operating state, we have no more than 100 ms. Since the chip is not the newest (Altera Cyclone IV GX), simply connecting to it a fast flash drive like EPCQ does not work. And we decided to use the FPP (Fast Passive Serial) mode by putting the CPLD Intel MAXV from the FPL (Flash Parallel Loader) outside. At startup, the CPLD loads data from the USB flash drive and generates FPP signals at its outputs.
 
However, before doing the planned, they collected a DIY-layout from what was at hand, and ...
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Organization of the bus infrastructure connecting the agents of the system interface STI version 1.0

Organization of the bus infrastructure connecting the agents of the system interface STI version 1.0The article describes the principles of building the infrastructure of a local system bus that connects agents of a single segment of the joint of a simple performer STI version 1.0 in the volume of a VLSI or FPGA crystal. The organization of the address decoder, data bus switchboards and the executor's selection is considered. An example of the description of the bus infrastructure of the STI segment in the language of Verilog is given. Variants of connection of performers to segments of the bus with a lower bit of data are offered.
 
 
The Simple Target Interface (STI) is a set of logic signals ...
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Synchronous system interface of interaction with peripheral blocks in the volume of a VLSI or FPGA crystal. STI 1.0

Synchronous system interface of interaction with peripheral blocks in the volume of a VLSI or FPGA crystal. STI 1.0The article proposes the organization of interaction of functional blocks in the volume of a VLSI crystal, namely: processor cores, DMA controllers and system bus bridges with peripheral blocks, such as: GPIO, SPI, I2C, UART controllers, timers and PWM pulse width modulators. A set of signals and a protocol for exchanging the joint of a simple performer-a local system interface that realizes the interaction of the listed blocks of the crystal-is considered. Examples of synthesized models of the GPIO controller and register file that support the described interface are given.
 
 
Since the mastering ...
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Configuring Sublime Text 3 to work with VHDL files

Working with VHDL in Sublime Text 3


 
The Sublime Text editor saves a lot of time when working with vhdl and verilog files. For those who did not work with editors like Sublime Text, Notepad ++, etc. I will describe the main useful functions of these editors:
 
 
 
multiple selection /editing of lines of code (pressing the middle mouse button or with the Ctrl key pressed)
 
setting of marks (bookmarks) in the code, helps to navigate in large files. (Ctrl + F2 or through the menu item Goto → Bookmarks)
 
the ability to divide the workspace into several windows (Alt + Shift + 2 or from the View ...[/h]
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FPGA-accelerators go into the clouds

FPGA-accelerators go into the clouds
 
 
The appearance of FPGA-accelerators on the market, which can be reprogrammed as many times as possible, and in a high-level language like "C", has become a real breakthrough in the niche of high-performance computing. But no less a breakthrough was the opportunity to use FPGA technology without buying these very expensive adapters (the price in Russia is from 25?000 rubles) - but simply renting a dedicated server with an accelerator in the provider's cloud.
Introduction in 3 paragraphs
 
Basic differences of FPGA from CPU, GPU
 
Applications FPGA ...
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About porting the project MIPSfpga

About porting the project MIPSfpga  
 
The transfer of software from one computer architecture to another in principle, with some reservations, is relatively simple. Here, such well-known tools as autoconf /automake /libtool /gnulib come to the rescue. To assemble the program from the sources on some Raspberry /ARM is as easy as on a PC with Ubuntu /x86-64.
 
 
And here is how to force the FPGA project developed for one card to work on another board? There, the FPGA itself can be different and on the board, completely different components can stand. A simple recompilation of the project is indispensable.
 
 
I'll tell you about my experience ...
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As I blakecoin the miner did

As I blakecoin the miner did  
 
I do not know how anyone, but I was shocked by the rapid rise of bitcoin in 2017. Now, of course, the excitement has already left, and in the 17th year, about crypto-currencies they talked and wrote to everyone who is not lazy.
 
 
I saw that people are trying to earn on crypto-currencies. Who knows how. Someone bought up video cards for all the savings and started independently to mine in the garage. Someone was investing in cloud mining. Someone is trying to organize their pool. Someone has started producing chocolate bitcoins, and some are producing mineral water:
 
 
...
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Asynchronous (self-timed) circuits. Calculation of logical functions directly in the event graph. Part 2

I will remind you that in first part it was about calculating simple implicants (conjunctions) for cyclic behaviors without parallelism, choice and multiple signals over three points (states).
 
 
Asynchronous (self-timed) circuits. Calculation of logical functions directly in the event graph. Part 2  
 
The task was for the implicant to cover the point 2 (i.e., it was equal to 1 in this state) and not go beyond the limits indicated by points 1 and 3 Moreover, the position of the left border of the implicant (to the left of point 2) is indifferent. The right border (to the right of point 2) should be shifted to the right as far as possible. The impossibility of calculating implicants means having a ...
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