3r33336. 3r3-31. Greetings, Habr! My name is Daniel Smirnov, I study in the graduate school of ITMO University, where in the programming and modeling laboratory our team is engaged in programmable electronics for projects related to fiber-optic sensors. The FPGA - Field Programmable Gate Array is used as the hardware base for the sensors. A couple of years ago, we found out that FPGA manufacturers are holding contests for engineering students. Since then, every year a team is formed from us to participate in this event, and since this year it turned out to be special, we decided to share how everything ...

I present to you the translation of the article Scott Wlaschin "Designing with types: Making illegal states unrepresentable" .
 
In this article, we will look at the key advantage of F # - the ability to "make invalid states ineffable" using a type system (the phrase borrowed from 3r3133. Yaron Minsky
).
 
Consider the type Contact . As a result, carried out refactoring It is much simpler:
 

    type Contact =
{
Name: Name;
EmailContactInfo: EmailContactInfo;
PostalContactInfo: PostalContactInfo;
}    

 

Now suppose that there is a simple ...

What is this all about?
 
I'll talk about how to build a model of actors using MailboxProcessor from the standard library, at what points to pay attention and on what pitfalls you can expect.
 

I do not claim the truth in the last resort. The code written here is not perfect, it can violate some principles and can be written better. But if you are new and want to deal with mailboxes, I hope this article will help you.

 

If you know everything about mailboxes and without me - you can be bored here.

 

Why actors?

 

For the sake of practice. I read about ...

 
With the development of microelectronics, rtl designs have become more and more. The re-usability of the code on verilog delivers a lot of inconvenience, even with the use of generate, macros and chips system verilog. Chisel, however, makes it possible to apply the full power of object and functional programming to the development of rtl, which is quite a welcome step, which can fill the lungs of light developers ASIC and FPGA.
 
In this article, we will give a brief overview of the main functional and consider some use cases, and also talk about the shortcomings of this language. In the future, if the ...

 
Part I
 
Part II
 
Part III
 
 
This is the full version of the previous article.
 
 
We design Little Man Computer in Verilog.
 
 
Article about LMC was on Habré.
 
 
Online simulator of this computer here .
 
 
Let's write the RAM module consisting of four (ADDR_WIDTH = 2) four-bit (DATA_WIDTH = 4) words. Data is loaded into RAM from data_in at adr when the clock signal clk arrives.
 
module R0 # (parameter ADDR_WIDTH = ? DATA_WIDTH = 4)
(
input clk, clock signal
input[ADDR_WIDTH-1:0]adr, address
input[DATA_WIDTH-1:0]data_in...[/DATA][/ADDR]

Hello!
 
Recently there was a task - to accelerate the loading of FPGA. From the appearance of power to the operating state, we have no more than 100 ms. Since the chip is not the newest (Altera Cyclone IV GX), simply connecting to it a fast flash drive like EPCQ does not work. And we decided to use the FPP (Fast Passive Serial) mode by putting the CPLD Intel MAXV from the FPL (Flash Parallel Loader) outside. At startup, the CPLD loads data from the USB flash drive and generates FPP signals at its outputs.
 
However, before doing the planned, they collected a DIY-layout from what was at hand, and ...

The article describes the principles of building the infrastructure of a local system bus that connects agents of a single segment of the joint of a simple performer STI version 1.0 in the volume of a VLSI or FPGA crystal. The organization of the address decoder, data bus switchboards and the executor's selection is considered. An example of the description of the bus infrastructure of the STI segment in the language of Verilog is given. Variants of connection of performers to segments of the bus with a lower bit of data are offered.
 
 
The Simple Target Interface (STI) is a set of logic signals ...

The article proposes the organization of interaction of functional blocks in the volume of a VLSI crystal, namely: processor cores, DMA controllers and system bus bridges with peripheral blocks, such as: GPIO, SPI, I2C, UART controllers, timers and PWM pulse width modulators. A set of signals and a protocol for exchanging the joint of a simple performer-a local system interface that realizes the interaction of the listed blocks of the crystal-is considered. Examples of synthesized models of the GPIO controller and register file that support the described interface are given.
 
 
Since the mastering ...

Working with VHDL in Sublime Text 3

 
The Sublime Text editor saves a lot of time when working with vhdl and verilog files. For those who did not work with editors like Sublime Text, Notepad ++, etc. I will describe the main useful functions of these editors:
 
 
 
multiple selection /editing of lines of code (pressing the middle mouse button or with the Ctrl key pressed)
 
setting of marks (bookmarks) in the code, helps to navigate in large files. (Ctrl + F2 or through the menu item Goto → Bookmarks)
 
the ability to divide the workspace into several windows (Alt + Shift + 2 or from the View ...[/h]

 
 
The appearance of FPGA-accelerators on the market, which can be reprogrammed as many times as possible, and in a high-level language like "C", has become a real breakthrough in the niche of high-performance computing. But no less a breakthrough was the opportunity to use FPGA technology without buying these very expensive adapters (the price in Russia is from 25?000 rubles) - but simply renting a dedicated server with an accelerator in the provider's cloud.
Introduction in 3 paragraphs
 
Basic differences of FPGA from CPU, GPU
 
Applications FPGA ...