A tenth-grader from Siberia wants to become a processor designer. Why shouldn't she make a FPGA neuro accelerator?

A tenth-grader from Siberia wants to become a processor designer. Why shouldn't she make a FPGA neuro accelerator?Yesterday I received a letter from a tenth-grader from Siberia, who wants to become a microprocessor developer. She has already received some results in this area - she added a multiplication instruction to the simplest schoolMIPS processor, synthesized it for the Intel FPGA MAX10 FPGA, determined the maximum frequency and increased performance of simple programs. She first did all this in the village of Burmistrovo, Novosibirsk Region, and then at a conference in Tomsk.
 
 
Now Dasha Krivoruchko (that is the name of the tenth grader) has moved to live in a Moscow boarding school and asks me what ...
+ 0 -

Development model on the example of Stack-based CPU

Development model on the example of Stack-based CPU3r33338. Have you ever wondered how the processor works? Yes, yes, exactly the one that is in your PC /laptop /smartphone. In this article I want to give an example of a self-invented processor with a design in the Verilog language. Verilog is not exactly the programming language it is similar to. This is the Hardware Description Language. The written code is not executed by anything (if you do not run it in the simulator, of course), but turns into the design of the physical circuit, or the view perceived by the FPGA (Field Programmable Gate Array).
https://github.com/IamMaxim/OurCPU ...
+ 0 -

Stack-based calculator on the Cyclone IV FPGA board

 3r31063. 3r3-31. 3r31036. Introduction
3r31050.  3r31063. We have been able to complete our project. We have chosen to make a stack-based calculator with reverse polish notation. FPGA board provided by the university. 3r31050.  3r31063. 3r31050.  3r31063. Stack-based calculator on the Cyclone IV FPGA board 3r31043. 3r31050.  3r31063. 3r31036. Basic design
3r31050.  3r31063. We formed a group of two people. Made it short, with the short line with the deadlines. This is what we come up with. We need to:
 3r31063. 3r31050.  3r31063. 3r3333.  3r31063.
Implement stack in the Verilog
 3r31063.
Learn how to work with the numpad
 3r31063.
Implement output through ...
+ 0 -

Features of window filtering on FPGA

Features of window filtering on FPGA 3r37474. 3r3-31. Hello! 3r33462.  3r37474. 3r33462.  3r37474. In this article we will discuss one important part of digital signal processing - window filtering of signals, in particular, on the FPGA. The article will show how to design classic windows of standard length and “long” windows from 64K to 16M + samples. The main development language is VHDL, the elemental base is modern FPGA Xilinx crystals of the last families: these are Ultrascale, Ultrascale +, 7-series. The article will show the implementation of CORDIC - the basic kernel for the configuration of window functions of any duration...
+ 0 -

How we participated in InnovateFPGA 2018 and did not win again

How we participated in InnovateFPGA 2018 and did not win again 3r33336. 3r3-31. Greetings, Habr! My name is Daniel Smirnov, I study in the graduate school of ITMO University, where in the programming and modeling laboratory our team is engaged in programmable electronics for projects related to fiber-optic sensors. The FPGA - Field Programmable Gate Array is used as the hardware base for the sensors. A couple of years ago, we found out that FPGA manufacturers are holding contests for engineering students. Since then, every year a team is formed from us to participate in this event, and since this year it turned out to be special, we decided to share how everything ...
+ 0 -

Designing Types: How to make invalid states ineffable

I present to you the translation of the article Scott Wlaschin "Designing with types: Making illegal states unrepresentable" .
 
In this article, we will look at the key advantage of F # - the ability to "make invalid states ineffable" using a type system (the phrase borrowed from 3r3133. Yaron Minsky
).
 
Consider the type Contact . As a result, carried out refactoring It is much simpler:
 
    type Contact =
{
Name: Name;
EmailContactInfo: EmailContactInfo;
PostalContactInfo: PostalContactInfo;
}

 

Now suppose that there is a simple ...

+ 0 -

As I wrote the snake on F # and the model of actors

What is this all about?
 
I'll talk about how to build a model of actors using MailboxProcessor from the standard library, at what points to pay attention and on what pitfalls you can expect.
 

I do not claim the truth in the last resort. The code written here is not perfect, it can violate some principles and can be written better. But if you are new and want to deal with mailboxes, I hope this article will help you.


 

If you know everything about mailboxes and without me - you can be bored here.


 

Why actors?


 

For the sake of practice. I read about ...

+ 0 -

Chisel - (not quite) a new approach to the development of digital logic

Chisel - (not quite) a new approach to the development of digital logic
 
With the development of microelectronics, rtl designs have become more and more. The re-usability of the code on verilog delivers a lot of inconvenience, even with the use of generate, macros and chips system verilog. Chisel, however, makes it possible to apply the full power of object and functional programming to the development of rtl, which is quite a welcome step, which can fill the lungs of light developers ASIC and FPGA.
 
In this article, we will give a brief overview of the main functional and consider some use cases, and also talk about the shortcomings of this language. In the future, if the ...
+ 0 -

Designing the CPU (CPU Design) LMC

Designing the CPU (CPU Design) LMC
 
Part I
 
Part II
 
Part III
 
 
This is the full version of the previous article.
 
 
We design Little Man Computer in Verilog.
 
 
Article about LMC was on Habré.
 
 
Online simulator of this computer here .
 
 
Let's write the RAM module consisting of four (ADDR_WIDTH = 2) four-bit (DATA_WIDTH = 4) words. Data is loaded into RAM from data_in at adr when the clock signal clk arrives.
 
module R0 # (parameter ADDR_WIDTH = ? DATA_WIDTH = 4)
(
input clk, clock signal
input[ADDR_WIDTH-1:0]adr, address
input[DATA_WIDTH-1:0]data_in...[/DATA][/ADDR]
+ 0 -

FPP via FPL: Accelerate the loading of FPGA

FPP via FPL: Accelerate the loading of FPGAHello!
 
Recently there was a task - to accelerate the loading of FPGA. From the appearance of power to the operating state, we have no more than 100 ms. Since the chip is not the newest (Altera Cyclone IV GX), simply connecting to it a fast flash drive like EPCQ does not work. And we decided to use the FPP (Fast Passive Serial) mode by putting the CPLD Intel MAXV from the FPL (Flash Parallel Loader) outside. At startup, the CPLD loads data from the USB flash drive and generates FPP signals at its outputs.
 
However, before doing the planned, they collected a DIY-layout from what was at hand, and ...
+ 0 -