This is the full version of the previous article.
We design Little Man Computer in Verilog.
Article about LMC was on Habré.
Online simulator of this computer here .
Let's write the RAM module consisting of four (ADDR_WIDTH = 2) four-bit (DATA_WIDTH = 4) words. Data is loaded into RAM from data_in at adr when the clock signal clk arrives.
module R0 # (parameter ADDR_WIDTH = ? DATA_WIDTH = 4)
input clk, clock signal