Features of window filtering on FPGA

3r37474. 3r3-31. Hello! 3r33462. 3r37474. 3r33462. 3r37474. In this article we will discuss one important part of digital signal processing - window filtering of signals, in particular, on the FPGA. The article will show how to design classic windows of standard length and “long” windows from 64K to 16M + samples. The main development language is VHDL, the elemental base is modern FPGA Xilinx crystals of the last families: these are Ultrascale, Ultrascale +, 7-series. The article will show the implementation of CORDIC - the basic kernel for the configuration of window functions of any duration, as well as the basic window functions. The article describes a design method using high-level C /C ++ languages in Vivado HLS. As usual, at the end of the article you will find a link to the source code of the project. 3r33462. 3r37474. 3r33462. 3r37474. CDRD: a typical signal flow pattern through DSP nodes for spectrum analysis tasks. 3r33462. 3r37474.

3r33462. 3r37474. 3r33434. Introduction 3r33420. 3r33462. 3r37474. Many people know from the “Digital Signal Processing” course that for an infinite in time sine wave signal, its spectrum is a delta function at the signal frequency. In practice, the spectrum of a real harmonic signal is equivalent to the function 3r33412. ~ sin (x) /x [/b] and the width of the main lobe depends on the duration of the ** signal conversion interval. T ** . This is due to the fact that we cannot integrate the signal on an infinite time interval, and the Fourier transform in discrete form, expressed in a finite sum, is limited in the number of samples. As a rule, the FFT length in modern digital FPGA processing devices takes the values 3r-3412. NFFT [/b] from 8 to several million points. In other words, the spectrum of the input signal is calculated in the interval ** T ** which in many cases equals ** NFFT ** . Limiting the signal on the interval ** T ** , we thereby impose a “window” of a rectangular shape, of duration ** T ** counts. Consequently, the resulting spectrum is the spectrum of a multiplied harmonic signal and a rectangular envelope. In DSP tasks, windows of various shapes have been invented for quite a long time, which, when applied to a signal in the time domain, can improve its spectral characteristics. A large number of various windows is primarily due to one of the main features of any window overlay. This feature is expressed in the relationship between the level of side lobes and the width of the central lobe. Known pattern: the stronger the suppression of side lobes, the wider the main lobe, and vice versa. 3r33462. 3r37474. 3r33462. 3r37474. One of the applications of window functions is the detection of weak signals against the background of stronger ones by suppressing the level of side lobes. The main window functions in DSP tasks are triangular, sinusoidal, Lanczos window, Hannah, Hamming, Blackman, Harris, Blackman-Harris, flat top window, Natall, Gauss, Kaiser window and many others. Most of them are expressed in a finite series by summing up the harmonic signals with specific weighting factors. Windows of complex shape are calculated by taking an exponent (Gauss window) or a modified Bessel function (Kaiser window), and will not be considered in this article. More information about window functions can be found in the literature, which I traditionally give at the end of the article. 3r33462. 3r37474. 3r33462. 3r37474. The following figure shows typical window functions and their spectral characteristics, built using Matlab CAD tools. 3r33462. 3r37474. 3r33462. 3r37474. CORDIC [/b] (the method “3r33232. digit by digit 3r3-33236.”) manages to design a lot of window functions, the formulas of which are expressed in terms of harmonic signals (Blackman-Harris, Hannah, Hamming, Nattala, etc.) 3rr3462. 3r37474. 3r33462. 3r37474. 3r33434. CORDIC

3r33462. 3r37474. CORDIC is a simple and convenient iterative method for calculating the rotation of the coordinate system, which allows computing complex functions by performing primitive addition and shift operations. Using the CORDIC algorithm, you can calculate the sin (x), cos (x) harmonic signals, find the atan (x) and atan2 (x, y) phase, hyperbolic trigonometric functions, rotate the vector, extract the number root, etc. 3r33462. 3r37474. 3r33462. 3r37474. At first, I wanted to take a ready-made CORDIC core and reduce the amount of work, but I have an old dislike for the Xilinx cores. After studying the repositories on the githaba, I realized that all the kernels represented are not suitable for a number of reasons (poorly documented and unreadable, not universal, made for a specific task or element base, 3r-39? written in verilog 3r3191., Etc.). Then I asked for a friend 3r3r888. lazifo

do this job for me. Of course, he coped with it, because the implementation of CORDIC is one of the simplest tasks in the field of DSP. But since I'm impatient, in parallel with his work I wrote 3r390. your bike 3r3391. its parameterized kernel. The main features are a configurable bit depth of the output signals of 3r33412. DATA_WIDTH [/b] and input normalized phase ** PHASE_WIDTH ** from -1 to ? the task of calculation accuracy ** PRECISION ** . The CORDIC core is made along a conveyor parallel circuit — at each clock cycle the core is ready to perform calculations and receive input samples. The kernel spends on computing the output sample of N clock cycles, the number of which depends on the bitness of the output samples (the greater the bit depth - the more iterations to calculate the output value). All calculations occur in parallel. Thus, CORDIC is the base kernel for creating window functions. 3r33462. 3r37474. 3r33462. 3r37474. 3r33434. Window functions

3r33462. 3r37474. In this article, I implement only those window functions that are expressed through harmonic signals (Hannah, Hamming, Blackman-Harris of a different order, etc.). What is needed for this? In general terms, the formula for constructing a window looks like a series of finite length. 3r33462. 3r37474. 3r33462. 3r37474. 3r31-10. 3r33462. 3r37474. 3r33462. 3r37474. A defined set of coefficients ** a [sub] k 3r3117. 3r33434. and the members of the row determines the name of the window. The most popular and frequently used is the Blackman-Harris window: of a different order (from 3 to 11). Below is a table of coefficients for Blackman-Harris windows: 3r37474. 3r33462. 3r37474. 3r37474. 3r33434. 3r37474. 3r33450. bh_win_7term - Blackman-Harris 7 order, a window with maximum suppression of the lateral locks. 3r37474. 3r33450. bh_win_5term - Blackman-Harris 5 order, includes a window with a flat top. 3r37474. 3r33450. bh_win_4term - Blackman-Harris 4 order, includes the window Nattala and Blackman-Nattala. 3r37474. 3r33450. bh_win_3term - Blackman-Harris 3 orders of magnitude, 3r37474. 3r33450. hamming_win - windows Hamming and Hannah. 3r37474.3r33462. 3r37474. The source code for the Blackman-Harris window component is 3 orders of magnitude: 3r37474. 3r33462. 3r37474.3r33232. entity bh_win_3term isgeneric (TD: time: = 0.5ns; -! Time delayPHI_WIDTH: integer: = 10; -! Signal period = 2 ^ PHI_WIDTHDAT_WIDTH: integer: = 16; -! Output data widthXSERIES: string: = "ULTRA" -! For 6/7 series: "7SERIES"; for ULTRASCALE: "ULTRA";); 3r37474. port (RESET: in std_logic; -! Global resetCLK: in std_logic; -! System clockAA0: in std_logic_vector (DAT_WIDTH-1 downto 0); - A0std_logic_vector (DAT_WIDTH-1 downto 0); - A1AA2: in std_logic_vector (DAT_WIDTH-1 downto 0); - A2ENABLE: in std_logic; -!! DAT_WIDTH-1 downto 0); -! OutputDT_VLD: out std_logic -! Output data valid); 3r37474. end bh_win_3term; 3r37474. 3r33462. 3r37474. 3r33462. 3r37474. In some cases, I used the library. UNISIM for embedding nodes. DSP48E1 and DSP48E2 into the project, which ultimately makes it possible to increase the speed of calculations due to pipelining inside these blocks, but as practice has shown, it is faster and easier to give vent to laziness and write something like P = A * B + C and indicate in the code the following directives: 3r37474. 3r33462. 3r37474.3r33232. attribute USE_DSP of: signal is "YES"; 3r33462. 3r37474. 3r33462. 3r37474. It works great and hard for the synthesizer sets the type of element on which the mathematical function is implemented. 3r33462. 3r37474. 3r33462. 3r37474. 3r33434. Vivado HLS3r33462. 3r37474. In addition, I implemented all the kernels using the tools 3r33412. Vivado HLS ** . Enumerate the main

**Benefits**Vivado HLS is a high speed of design (3r3323235. Time-to-market [/i] ) In high-level C or C ++ languages, fast modeling of developed nodes due to the lack of the concept of clock frequency, flexible configuration of solutions (in terms of resources and performance) by the introduction of pragmas and directives in the project, as well as the low threshold of entry for developers in high-level languages. The main disadvantage is the non-optimal cost of FPGA resources in comparison with the classical approach. Also, it is not possible to achieve those speeds of work that are provided by the classic old RTL methods (VHDL, Verilog, SV). Well, the biggest 3r33412. lack of [/b] - this is a dance with a tambourine, but this is characteristic of the entire CAD system from Xilinx. (Note: in the Vivado HLS debugger and in the real C ++ model, different results were often obtained, since the Vivado HLS works crookedly when using the advantages of 3r-3235. Arbitrary precision 3r-3636.). 3r33462. 3r37474. 3r33462. 3r37474. The following picture shows the log of the synthesized CORDIC core in Vivado HLS. It is quite informative and displays a lot of useful information: the number of resources used, the user interface of the kernel, cycles and their properties, the delay for calculations, the interval for calculating the output value (important when designing sequential and parallel circuits): 3r3622. 3r37474. 3r33462. 3r37474. 3r33462. 3r37474. 3r33462. 3r37474. Result of work of Vivado HLS: the synthesized RTL-kernel created from the C-code. The log shows that, according to temporary analysis, the kernel successfully passes all restrictions: 3r3-33462. 3r37474. 3r37474. 3r33462. 3r37474. 3r33462. 3r37474. 3r33462. 3r37474. By iteratively calculating the value of Z, in parallel, the calculation of the values of X and Y occurs. The process of cyclically searching for output values on HDL: 3r-3462. 3r37474. 3r33462. 3r37474.

3r33232. constant ROM_LUT: rom_array: = (

x "400000000000", x "25C80A3B3BE6", x "13F670B6BDC7", x "0A2223A83BBB",

x "05161A861CB1", x "105 a, 201? a 201? an ??? ??? ??? ??? ??? 300 ,

X "00517CA68DA2", x "0028BE5D7661", x "00145F300123", x "000A2F982950",

X "000517CC19C0", x "00028BE60D83", and then you will be using the same programs to set the preferences for the rest of your preferences and your preferences. ", x" 000028BE60DC ", x" 0000145F306E ", x" 00000A2F9837 ",

x" 00000517CC1B ", x" 0000028BE60E ", x" 00000145F307 ", x" 000000A2F983 ",

x" 000000517CC2 ", x" 00000028BE61 ", x" 000000145F30 ", x" 0000000A2F98 ", 3r33474. X" 0000000517CC ", x" 000000028BE6 ", x" 0000000145F3 ", x" 00000000A2FA ",

X" 0000000052551552555515?) ", x" 00000000145F ", x" 000000000A30 ",

x" 000000000518 "," 00000000028C "x , x "00000000000A",

x "000000000005", x "000000000003", x "000000000001", x "000000000000"

); 3rr7474. reset = '1') then

---- Reset sine /cosine /angle vector ----

sigX <= (others => (others => '0'));

sigY <= (others => (others => '0 '));

SigZ <= (others => (Others =>' 0 ')); 3rrr7474. Elsif rising_edge (clk) then

- calculate sine & cosine ----

lpXY: for ii in 0 to DATA_WIDTH-2 l oop

if (sigZ (ii) (sigZ (ii) 'left) =' 1 ') then

sigX (ii + 1) <= sigX(ii) + sigY(ii)(DATA_WIDTH+PRECISION-1 downto ii);

sigY (ii + 1) <= sigY(ii) - sigX(ii)(DATA_WIDTH+PRECISION-1 downto ii);

else

sigX (ii + 1) <= sigX(ii) - sigY(ii)(DATA_WIDTH+PRECISION-1 downto ii);

sigY (ii + 1) 3r33336. end if; 3r37474. end loop; 3r37474. ---- calculate phase ----

lpZ: for ii in 0 to DATA_WIDTH-2 loop

if (sigZ (ii) (sigZ (ii) 'left) =' 1 ') then

sigZ (ii + 1) <= sigZ(ii) + ROM_TABLE(ii);

else

sigZ (ii + 1) <= sigZ(ii) - ROM_TABLE(ii);

end if; 3r37474. end loop; 3r37474. end if; 3r37474. end process; 3r37474.

3r33462. 3r37474. 3r33462. 3r37474. In C ++, the Vivado HLS code looks almost the same, but the record is several times shorter: 3r33434. 3r37474. 3r33462. 3r37474.

` //Unrolled loop //`

int k; 3r37474. stg: for (k = 0; k < NWIDTH; k++) {

#pragma HLS UNROLL

ifr (z[k] < 0) {

x[k+1]= x[k]+ k (2y2) x[k]k);

z[k+1]= z[k]+ lut_angle[k], 3rrr7474.} else {

x[k+1]= x w2w2w? a. y[k]+ (x[k]k);

z[k+1]= z[k]-

})) 3r37474. 3r33462. 3r37474. As you can see, the same cycle with shift and additions is used. However, by default all cycles in Vivado HLS are “minimized” and are executed sequentially, as it was intended for the C ++ language. Introduction of the pragma 3r33412. HLS UNROLL [/b] or ** HLS PIPELINE ** converts sequential calculations to parallel ones. This leads to an increase in FPGA consumed resources, however, it allows you to calculate and submit new values to the core at each clock cycle. 3r33462. 3r37474. 3r33462. 3r37474. 3r33434. Features implementation 3r33420. 3r33462. 3r37474. Since the calculations are performed in a fixed point format, the window functions have a number of features that must be considered when designing DSP systems on a FPGA. For example, the greater the data width of the window function - the better the overlay accuracy of the window. On the other hand, if the window function is insufficiently small, distortion will be introduced into the resulting waveform, which will affect the quality of the spectral characteristics. For example, a window function must have at least 20 bits when multiplied by a signal of 2 ^ 20 duration = 1M samples. 3r33462. 3r37474. 3r33462. 3r37474. 3r33434. Conclusion 3r33420. 3r33462. 3r37474. This article shows one of the ways to design window functions without using external memory or block FPGA memory. A method is provided for engaging only the logical resources of the FPGA (and in some cases, DSP blocks). Using the CORDIC algorithm, it is possible to obtain window functions of any bit depth (within reasonable limits), of any length and order, and therefore - to have a set of practically any spectral characteristics of the window. 3r33462. 3r37474. 3r33462. 3r37474. In one of the works, I managed to get a stable operating Blackman-Harris window function 5 and 7 on 1M samples at a frequency of ~ 375 MHz, and also to make a generator of turning factors for a CORDIC based FFT at a frequency of ~ 400 MHz. Used FPGA crystal: Kintex Ultrascale + (xcku11p-ffva1156-2-e). 3r33462. 3r37474. 3r33462. 3r37474. Link to 3r3114. project 3r33412. github [/b] here is

. The project contains a mathematical model in Matlab, source codes of window functions and CORDIC on VHDL, as well as models of listed window functions in C ++ for Vivado HLS. 3r33462. 3r37474. 3r33462. 3r37474. 3r33434. Useful articles

3r33462. 3r37474. 3r33434. 3r37474. 3r33450. 3r33426. DSPLib window functions

3r37474. 3r33450. Some window functions DSPlib

3r37474. 3r33450. Expanded article on the Wiki on window filtering

3r37474. 3r33450. Wiki article on CORDIC

3r37474. 3r33450. Vivado HLS Userguide

3r37474. 3r33450. Article about the spectral analysis on Habré

3r37474.

3r33462. 3r37474. I also advise a very popular book on DSP - Ifericher E., Jervis B. Digital Signal Processing. Practical approach 3r33462. 3r37474. 3r33462. 3r37474. Thanks for attention! 3r33470. 3r37474. 3r37474.

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#### Programming microcontrollers / Mathematics / Algorithms / FPGA

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