3r3-31. 3r31298.  
3r31290. In the life of each pleisovod there comes a time when you need to write your own configuration file loader in the FPGA. I had to participate in the development of an educational stand for the department of a technical university. The stand is designed to study digital signal processing, although in this article it does not really matter. And what matters is that the stand is based on the FPGA (Altera Cyclone IV), on which, according to the idea of ​​the stand's author, students assemble all kinds of DSP schemes. The stand is connected to the computer via USB. Required to download FPGA from a computer via USB. 3r31298.  
The decision to connect to a PC to use FTDI in its dual channel form - FT2232H was made. One channel will be used to configure the FPGA, the other can be used for high-speed exchange in FIFO mode. Command Processor for MPSSE and MCU Host Bus Emulation Mode 3r3-331329. . 3r31298.  
MPSSE tuning is reduced to setting the data transfer rate, direction and initial states of the I /O lines. 3r31298.  
Consider setting the MPSSE processor's transfer rate. The setting for chips with support for Full-speed mode only (FT2232 3r33450. D3r3451.) And chips with High-speed (FT2232
H
, FT232H, FT4232H) occurs somewhat differently. The outdated FT2232D uses a 12 MHz clock and 60 MHz in modern ones. Hence the formula for calculating the data transfer rate:
3r31298.  
3r31290. 3r31293. 3r31290.
3r33460. 3r31293. 3r31298.  
3r31290. where
f _core 3r31158. - FTDI core frequency,
Divisor
- two-byte divider, which, in fact, sets the clocking frequency of data. 3r31298.  
As a result, if the divisor is zero, then the maximum data transfer rate will be 30 Mbps, and the minimum data transfer rate will be at 65535 divider - 458 bps. 3r31298.  
Calculation of the divisor will charge the preprocessor The macro returns the divisor:
3r31298.  
3r31277. 3r31167. #define FCORE 60000000ul
#define MPSSE_DATA_SPEED_DIV (data_speed) ((FCORE /(2 * data_speed)) -1) 3r31228. 3r31285. 3r31298.  
3r31290. And these two macros return the high and low bytes of the divisor, respectively:
3r31298.  
3r31277. 3r31167. #define MPSSE_DATA_SPEED_DIV_H (data_speed) ((MPSSE_DATA_SPEED_DIV (data_speed)) 8) 3r31343. #define MPSSE_DATA_SPEED_DIV_L (data_speed) 3r31343. (MPSSE_DATA_SPEED_DIV (data_speed) - (MPSSE_DATA_SPEED_DIV_H (data_speed) 8)) 3r31228. 3r31285. 3r31298.  
3r31290. In addition, it should be noted that in modern chips for compatibility with the old man FT2232D there is an additional divider by ? which turns 60 MHz into 12 MHz. This divider is activated by default, in our case it should be disabled. 3r31298.  
We find the corresponding op-code (0x8A) and a helmet command to the processor:
3r31298.  
3r31162. 3r31163. Listing sending command [/b] 3r31165. 3r31277. 3r31167. BYTE byOutputBuffer[8], byInputBuffer[8];
DWORD dwNumBytesToRead, dwNumBytesSent = ? dwNumBytesRead = 0;
byOutputBuffer[0]= 0x8A;
ftStatus = FT_Write (ftHandle, byOutputBuffer, ? & dwNumBytesSent);
Sleep (2); //Wait for data to be transmitted and status
ftStatus = FT_GetQueueStatus (ftHandle, & dwNumBytesToRead);
ftStatus | = FT_Read (ftHandle, byInputBuffer, dwNumBytesToRead, & dwNumBytesRead);
if (ftStatus! = FT_OK)
{
printf ("Errorrn");
return FT_OTHER_ERROR;
}
else if (dwNumBytesToRead> 0)
{
printf ("dwNumBytesToRead =% d:", dwNumBytesToRead);
for (int i = 0; i 3r33838. printf ("% 02Xh", byInputBuffer[i]); 3r3131343. 3r313343. printf ("rn"); 3r3r1343. return
 
3r31290. As an experiment, instead of the actual command 0x8A, send the value 0xFE, which does not correspond to any op-code, console output: 3r31293. 3r31298.  
3r31277. 3r31278. dwNumBytesToRead = 2: FAh FEh 3r31285. 3r31298.  
3r31290. The processor returned two bytes, the byte "bad command" - 0xFA and the value of this "bad" command. Thus, by sending several commands at once, we will be able not only to track the fact of the error itself, but also to understand on which command this error occurred. 3r31298.  
In order not to deal with "magic numbers" in the future, we will arrange all op-code in the form of constants and put it in a separate header file. 3r31298.  
To fully configure the mode, you need to set the direction of the I /O lines and their default value. Let us turn to the concept of connection. In order not to clutter up an already bloated article, I crossed out a fragment of the scheme of interest:
3r31298.  
3r33558. 3r31298.  
3r31290. Lines
DCLK
, 3r31157. DATA[0]3r31158. , 3r31157. nCONFIG
must be configured as output lines
nSTATUS
, 3r31157. CONF_DONE
- as inputs. According to the diagram, we determine what initial states the lines should have. For clarity, the pinout of the scheme is summarized in the table:
3r31298.  
3r33838.  
 
3r3958.  
3r33879. FPGA pin
 
3r33879. Pin Name 3r38080.  
3r33879. Pin
 
3r33879. MPSSE
 
3r33879. Direction
 
3r33879. default
 
3r33966.  
3r3884.  
3r3886.  
3r3958.  
3r3393963. DCLK
 
3r3393963. BDBUS0
 
3r3393963. 38
 
3r3393963. TCK /SK
 
3r3393963. Out
 
3r3393963. 0
 
3r33966.  
3r3958.  
3r3393963. DATA[0]
 
3r3393963. BDBUS1
 
3r3393963. 39
 
3r3393963. TDI /DO
 
3r3393963. Out
 
3r3393963. 1
 
3r33966.  
3r3958.  
3r3393963. nCONFIG
 
3r3393963. BDBUS2
 
3r3393963. 40
 
3r3393963. TDO /DI
 
3r3393963. Out
 
3r3393963. 1
 
3r33966.  
3r3958.  
3r3393963. nSTATUS
 
3r3393963. BDBUS3
 
3r3393963. 41
 
3r3393963. TMS /CS 3r3393964.  
3r3393963. In
 
3r3393963. 1
 
3r33966.  
3r3958.  
3r3393963. CONF_DONE
 
3r3393963. BDBUS4
 
3r3393963. 43
 
3r3393963. GPIOL0
 
3r3393963. In
 
3r3393963. 1
 
3r33966.  
 
3r31298.  
3r31290. All used lines are located on the low byte of the MPSSE port. To set the value, use op-code 0x80. This command assumes two arguments: the first following the op-code byte is a bitwise value, and the second is the direction (one is the port to be output, zero is the port to be input). 3r31298.  
As part of the fight against the "magic number", all the ordinal numbers of the lines and their default values ​​will be in the form of constants:
3r31298.  
3r31162. 3r31163. Define ports [/b] 3r31165. 3r31277. 3r31167. #define PORT_DIRECTION (0x07)
#define DCLK (0)
#define DATA0 (1)
#define N_CONFIG (2)
#define N_STATUS (3)
#define CONF_DONE (4)
//initial states of the MPSSE interface
#define DCLK_DEF (1)
#define DATA0_DEF (0)
#define N_CONFIG_DEF (1)
#define N_STATUS_DEF (1)
#define CONF_DONE_DEF (1) 3r31285.
3r31298.  
3r31290. It remains only to make sure that the TDI - TDO loop is disabled (can be activated for testing) and issue a separate function: 3r31293. 3r31298.  
3r31162. 3r31163. Listing function MPSSE_setup [/b] 3r31165. 3r31277. 3r31167. static FT_STATUS
MPSSE_setup ()
{
DWORD dwNumBytesToSend, dwNumBytesSent, dwNumBytesToRead, dwNumBytesRead;
BYTE byOutputBuffer[8], byInputBuffer[8];
FT_STATUS ftStatus;
//Multple commands can be sent to the MPSSE with one FT_Write
dwNumBytesToSend = 0; //Start with a fresh index
byOutputBuffer[dwNumBytesToSend++]= MPSSE_CMD_DISABLE_DIVIDER_5;
byOutputBuffer[dwNumBytesToSend++]= MPSSE_CMD_DISABLE_ADAPTIVE_CLK;
byOutputBuffer[dwNumBytesToSend++]= MPSSE_CMD_DISABLE_3PHASE_CLOCKING;
ftStatus = FT_Write (ftHandle, byOutputBuffer, dwNumBytesToSend, & dwNumBytesSent);
dwNumBytesToSend = 0; //Reset output buffer pointer
//Set TCK frequency
//Command to set clock divisor:
byOutputBuffer[dwNumBytesToSend++]= MPSSE_CMD_SET_TCK_DIVISION;
//Set ValueL of clock divisor:
byOutputBuffer[dwNumBytesToSend++]= MPSSE_DATA_SPEED_DIV_L (DATA_SPEED);
//Set 0xValueH of clock divisor:
byOutputBuffer[dwNumBytesToSend++]= MPSSE_DATA_SPEED_DIV_H (DATA_SPEED);
ftStatus | = FT_Write (ftHandle, byOutputBuffer, dwNumBytesToSend, & dwNumBytesSent);
dwNumBytesToSend = 0; //Reset output buffer pointer
//Set initial states of the MPSSE interface
//- low byte, both pin directions and output values ​​
/* 3r31343. | FPGA pin | Pin Name | Pin | MPSSE | Dir | def |
| --------- | -------- | --- | ------ | --- | --- |
| DCLK | BDBUS0 | 38 | TCK /SK | Out | 0 |
| DATA[0]| BDBUS1 | 39 | TDI /DO | Out | 1 |
| nCONFIG | BDBUS2 | 40 | TDO /DI | Out | 1 |
| nSTATUS | BDBUS3 | 41 | TMS /CS | In | 1 |
| CONF_DONE | BDBUS4 | 43 | GPIOL0 | In | 1 |
* /
//Configure data bits low-byte of MPSSE port:
byOutputBuffer[dwNumBytesToSend++]= MPSSE_CMD_SET_DATA_BITS_LOWBYTE;
//Initial state config above:
byOutputBuffer[dwNumBytesToSend++]= (DCLK_DEF DCLK) | (DATA0_DEF DATA0)
| (N_CONFIG_DEF N_CONFIG) | (N_STATUS_DEF N_STATUS)
| (CONF_DONE_DEF CONF_DONE);
//Direction config above:
byOutputBuffer[dwNumBytesToSend++]= PORT_DIRECTION;
ftStatus | = FT_Write (ftHandle, byOutputBuffer, dwNumBytesToSend, & dwNumBytesSent);
//Send off the low GPIO config commands
dwNumBytesToSend = 0; //Reset output buffer pointer
//Set initial states of the MPSSE interface
//- high byte, all input, Initial State - 0.
//Send off the high GPIO config commands:
byOutputBuffer[dwNumBytesToSend++]= MPSSE_CMD_SET_DATA_BITS_HIGHBYTE;
byOutputBuffer[dwNumBytesToSend++]= 0x00;
byOutputBuffer[dwNumBytesToSend++]= 0x00;
ftStatus | = FT_Write (ftHandle, byOutputBuffer, dwNumBytesToSend, & dwNumBytesSent);
//Disable loopback:
byOutputBuffer[dwNumBytesToSend++]= MPSSE_CMD_DISABLE_LOOP_TDI_TDO;
ftStatus | = FT_Write (ftHandle, byOutputBuffer, dwNumBytesToSend, & dwNumBytesSent);
Sleep (2); //Wait for data to be transmitted and status
ftStatus = FT_GetQueueStatus (ftHandle, & dwNumBytesToRead);
ftStatus | = FT_Read (ftHandle, byInputBuffer, dwNumBytesToRead, & dwNumBytesRead);
if (ftStatus! = FT_OK)
{
printf ("Unknown error in initializing the MPSSErn");
return FT_OTHER_ERROR;
}
else if (dwNumBytesToRead> 0)
{
printf ("Error in initializing the MPSSE, bad code: rn");
for (int i = 0; i 3r33838. printf ("% 02Xh", byInputBuffer[i]); 3r3131343. 3r313343. printf ("rn");
return}
3r3r131339.
 
3r33852. Item 4. We implement the download protocol
3r31298.  
3r31290. It seems everything is ready for practical experiments. First, we verify that initialization is performed correctly, in the main body of the program, we will call 3r3-31278. MPSSE_open () and 3r31278. MPSSE_setup () , and before closing the device ( FT_Close ) we place an empty getchar () . Run the program and use the oscilloscope to make sure that the default levels are set on all the PS lines. By changing the value of these levels in the initialization (nothing terrible will happen with the FPGA), we make sure that the desired MPSSE processor is really valid - everything works adequately and you can proceed to the data transfer. 3r31298.  
Sequential sending and receiving of data is performed in command mode using the same op-code. The first byte of the command is the op-code, which determines the type of operation, followed by the length of the transmitted or received sequence and, if it is a transfer, the data itself. The MPSSE processor can transmit and receive data, also do it simultaneously. Transmission may be either the least significant bit forward (LSB) or the most significant (MSB). Data transmission can occur either on the leading or trailing edge of clock pulses. For each combination of options there is its own op-code, each bit of op-code describes the operation mode: 3r31298.  
3r33838.  
line. DATA[0]3r31158. , the red channel - DCLK . For clarity, the sequential decoding function is activated and the binary code is shown directly below the signal. As you can see, they sent it, they received it. 3r31298.  
At this stage, we can say that we have implemented an SPI interface (well, almost). In order to turn it into PS, you need to configure the work with flags. Three flags nCONFIG , 3r31157. nSTATUS , 3r31157. CONF_DONE . The first flag is the output, we must control it from the application, the other two - the inputs, we must be able to read them. 3r31298.  
Function MPSSE_get_lbyte reads the low byte of the whole, in order to obtain the value of the desired flag, you can use a bit mask. 3r31293. 3r31298.  
3r31162. 3r31163. Listing function MPSSE_get_lbyte [/b] 3r31165. 3r31277. 3r31167. static FT_STATUS
MPSSE_get_lbyte (BYTE * lbyte)
{
DWORD dwNumBytesToSend, dwNumBytesSent, dwNumBytesToRead, dwNumBytesRead;
BYTE byOutputBuffer[8];
FT_STATUS ftStatus;
dwNumBytesToSend = 0;
byOutputBuffer[dwNumBytesToSend++]= MPSSE_CMD_GET_DATA_BITS_LOWBYTE;
ftStatus = FT_Write (ftHandle, byOutputBuffer, dwNumBytesToSend, & dwNumBytesSent);
Sleep (2); //Wait for data to be transmitted and status
ftStatus = FT_GetQueueStatus (ftHandle, & dwNumBytesToRead);
ftStatus | = FT_Read (ftHandle, lbyte, dwNumBytesToRead, & dwNumBytesRead);
if ((ftStatus! = FT_OK) & (dwNumBytesToRead! = 1))
{
printf ("Error read Lbytern");
return FT_OTHER_ERROR; //Exit with error
}
return FT_OK;
} 3r31285. 3r31298.  
3r31290. Unfortunately, among op-code there are no commands that allow modifying a bit in a port without modifying the entire byte. Therefore, before setting a value to a single output line, you need to read the entire byte, modify the required bit and then write it to the port. Not a very beautiful decision, but let it be. Let's make the code in function MPSSE_set_lbyte : 3r31298.  
3r31162. 3r31163. Listing function MPSSE_set_lbyte [/b] 3r31165. 3r31277. 3r31167. static FT_STATUS
MPSSE_set_lbyte (BYTE lb, BYTE mask)
{
DWORD dwNumBytesToSend, dwNumBytesSent;
BYTE byOutputBuffer[8]lbyte;
FT_STATUS ftStatus;
ftStatus = MPSSE_get_lbyte (& lbyte);
if (ftStatus! = FT_OK)
return ftStatus;
//Set to zero the bits selected by the mask:
lbyte & = ~ mask;
//Setting zero is not selected by the mask bits:
lb & = mask;
lbyte | = lb;
dwNumBytesToSend = 0;
//Set data bits low-byte of MPSSE port:
byOutputBuffer[dwNumBytesToSend++]= MPSSE_CMD_SET_DATA_BITS_LOWBYTE;
byOutputBuffer[dwNumBytesToSend++]= lbyte;
byOutputBuffer[dwNumBytesToSend++]= PORT_DIRECTION;
ftStatus = FT_Write (ftHandle, byOutputBuffer, dwNumBytesToSend, & dwNumBytesSent);
if ((ftStatus! = FT_OK) & (dwNumBytesSent! = 1))
{
printf ("Error set Lbytern");
return FT_OTHER_ERROR;
}
return FT_OK;
} 3r31285. 3r31298.  
3r31290. All the bricks are assembled, burned and ready for laying. The program's algorithm is as follows: open FTDI; we activate and configure MPSSE; open the rbf file for reading, feed to the line. nCONFIG logical zero, waiting for a logical zero on the line N_STATUS ; sequentially read the contents of the rbf file and transfer it to the FPGA after the file is transferred completely, we wait for the logical unit on line 3r31157. CONF_DONE . In all examples and manuals, after working with the MPSSE processor, before closing the FTDI, it is recommended to switch it to the default mode. However, the flag nCONFIG will turn out to be zero and the FPGA will “forget” everything that we have loaded into it, so after working out the algorithm we leave everything as it is, just close the file and the port. 3r31293. 3r31298.  
3r31162. 3r31163. Listing function main [/b] 3r31165. 3r31277. 3r31167. int main (int argc, char * argv[])
{
FT_STATUS ftStatus;
BYTE lowByte;
DWORD numDevs; //create the device information list
if (argv[1]== NULL)
{
printf ("NO filern");
return -1;
}
frbf = fopen (argv[1], "rb");
if (frbf == NULL)
{
printf ("Error open rbfrn");
return -1;
}
ftStatus = FT_CreateDeviceInfoList (& numDevs);
if ((numDevs == 0) || (ftStatus! = FT_OK))
{
printf ("Error. FTDI devices not found in the systemrn");
return -1;
}
ftStatus = MPSSE_open ("LESO7 B");
if (ftStatus! = FT_OK)
{
printf ("Error in MPSSE_open% dn", ftStatus);
EXIT (-1);
}
MPSSE_setup ();
if (ftStatus! = FT_OK)
{
printf ("Error in MPSSE_setup% dn", ftStatus);
EXIT (-1);
}
printf ("nConfig -> 0rn");
MPSSE_set_lbyte (? 1 N_CONFIG);
printf ("nConfig -> 1rn");
MPSSE_set_lbyte (1 N_CONFIG, 1 N_CONFIG);
if (MPSSE_get_lbyte (& lowByte)! = FT_OK)
{
EXIT (-1);
}
if (((lowByte N_STATUS) & 1) == 0)
{
printf ("Error. FPGA is not respondingrn");
EXIT (-1);
}
int i = 0;
size_t readBytes = 0;
//Send the configuration file:
do
{
readBytes = fread (buff, ? MPSSE_PCK_SEND_SIZE, frbf);
if (MPSSE_send (buff, readBytes)! = FT_OK)
EXIT (-1);
putchar ('*');
if (! ((++ i)% 16)) printf ("rn");
}
while (readBytes == MPSSE_PCK_SEND_SIZE);
printf ("rn");
memset (buff, 0x0? sizeof (buff));
MPSSE_send (buff, 1); //really no one will notice this strange line?
printf ("Load completern");
//wait CONF_DONE set
//A low-to-high transition on the CONF_DONE pin indicates that the configuration is
//complete and initialization of the device can begin.
i = 0;
do
{
if (MPSSE_get_lbyte (& lowByte)! = FT_OK)
{
printf ("Error read CONF_DONErn");
EXIT (-1);
}
if (i ++> TIMEOUT_CONF_DONE) 3r3r1343. {
printf ("Error CONF_DONErn");
EXIT (-1);
}
Sleep (2);
}
while (((lowByte CONF_DONE) & 1) == 0);
printf ("Configuration completern");
FT_Close (ftHandle);
fclose (frbf);
} 3r31285. 3r31298.  
3r31290. Example of running the program: 3r31293. 3r31298.  
3r31277. 3r31278. Open "LESO7 B" OK
nConfig -> 0
nConfig -> 1
**
Load complete
Configuration complete 3r31285.
3r31298.  
3r31290. The utility successfully loads the rbf-file into the FPGA. FPGA happily blinks LEDs. We set the maximum data transfer rate to 30 Mbps and make sure that the software works. 3r31298.  
The disadvantages of the solution include the fact that there is no possibility of debugging and the resulting bootloader is still not JTAG. 3r31293. 3r31298.  
3r31296. Materials
3r31298.  
3r31300.  
3r? 31303. FTDI-MPSSE-Altera PS
. Repository with the project.
 
3r? 31308. Training stand for DSP
. Iron for experience. There you will find the complete schematic diagram of the device.
 
[leech=http://www.ftdichip.com/Support/Documents/ProgramGuides/D2XX_Programmer] Software Application Development D2XX Programmer's Guide 3r3-331329. . This is where the development of software for FTDI begins. API Guide D2XX.
 
3r31318. FTDI MPSSE Basics. Application Note AN_135 3r3-331329. . The name is clear. Basics of FTDI MPSSE. Description of the essence of the mode with code examples.
 
Command Processor for MPSSE and MCU Host Bus Emulation Modes. Application Note AN_108 3-3331329. . Handbook of op-code. Without it in any way.
 
D2XX Drivers . FTDI driver.
 
! function (e) {function t (t, n) {if (! (n in e)) {for (var r, a = e.document, i = a.scripts, o = i.length; o-- ;) if (-1! == i[o].src.indexOf (t)) {r = i[o]; break} if (! r) {r = a.createElement ("script"), r.type = "text /jаvascript", r.async =! ? r.defer =! ? r.src = t, r.charset = "UTF-8"; var d = function () {var e = a.getElementsByTagName ("script")[0]; e.parentNode.insertBefore (r, e)}; "[object Opera]" == e.opera? a.addEventListener? a.addEventListener ("DOMContentLoaded", d,! 1): e.attachEvent ("onload", d ): d ()}}} t ("//mediator.mail.ru/script/2820404/"""_mediator") () (); 3r31337.