3r3-31. In previous part 3r3689. we looked at the evolution of interrupt delivery from devices in x86 systems (PIC → APIC → MSI), the general theory, and all the necessary terms. 3r33770.  
3r33770.  
In this practical part, we will look at how to roll back to using outdated interrupt delivery methods in Linux, namely, consider the kernel boot options:
 
3r33770.  
3r33737.  
3r3756. pci = nomsi
 
3r3756. noapic
 
3r3756. nolapic
 
3r3769. 3r33770.  
We will also look at the order in which the OS looks at the interrupt routing tables (ACPI /MPtable /$ PIR) and what effect it will have on adding load options: 3r-3770.  
3r33770.  
3r33737.  
3r3756. pci = noacpi
 
3r3756. acpi = noirq
 
3r3756. acpi = off
 
3r3769. 3r33770.  
You may have tried combinations of all these options when a device did not work due to a problem with interrupts. Let us examine what exactly they are doing and how they change the output /proc /interrupts. 3r33770.  
3r33770.  
3r3694. Download without additional options
3r33770.  
Watch the interrupt in this article we will be on a custom motherboard with Intel Haswell i7 with the lynxPoint-LP chipset running 3r3354. coreboot
. 3r33770.  
3r33770.  
We will display information about interruptions via the command 3r33770.  
3r33770.  
3r3675. cat /proc /interrupts
3r33770.  
Output at boot without additional options:
 
3r33770.  
3r3675.
CPU0 CPU1 CPU2 CPU3
0: ??? 0 IO-APIC-edge timer
1: ??? 1 IO-APIC-edge i8042
8: ??? 1 IO-APIC-edge rtc0
9: ??? 0 IO-APIC-fasteoi acpi
12: ??? 1 IO-APIC-edge
23: ??? 10 IO-APIC-fasteoi ehci_hcd: usb1
56: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
57: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
58: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
59: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
60: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
61: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
62: ??? 3454 PCI-MSI-edge ahci
63: ??? 0 PCI-MSI-edge eth59
64: ??? 832 PCI-MSI-edge eth59-rx-0
65: ??? 1309 PCI-MSI-edge eth59-rx-1
66: 1???? PCI-MSI-edge eth59-rx-2
67: ??? 2 PCI-MSI-edge eth59-rx-3
68: ??? 0 PCI-MSI-edge eth59-tx-0
69: ??? 205 PCI-MSI-edge eth59-tx-1
70: ??? 0 PCI-MSI-edge eth59-tx-2
71: ??? 50 PCI-MSI-edge eth59-tx-3
72: ??? 0 PCI-MSI-edge eth58
73: ??? 152 PCI-MSI-edge eth58-rx-0
74: ??? 0 PCI-MSI-edge eth58-rx-1
75: 2 3?117 2 PCI-MSI-edge eth58-rx-2
76: ??? 0 PCI-MSI-edge eth58-rx-3
77: ??? 149 PCI-MSI-edge eth58-tx-0
78: ???? PCI-MSI-edge eth58-tx-1
79: ??? 34 PCI-MSI-edge eth58-tx-2
80: ??? 0 PCI-MSI-edge eth58-tx-3
81: ??? 101 PCI-MSI-edge snd_hda_intel
82: ??? 224 PCI-MSI-edge i915
83: ??? 15 PCI-MSI-edge snd_hda_intel
NMI: ??? 0 Non-maskable interrupts
LOC: ??? 3499 Local timer interrupts
SPU: ??? 0 Spurious interrupts
PMI: ??? 0 Performance monitoring interrupts
IWI: ??? 111 IRQ work interrupts
RTR: ??? 0 APIC ICR read retries
RES: ??? 1946 Rescheduling interrupts
CAL: ??? 559 Function call interrupts
TLB: ??? 251 TLB shootdowns
TRM: ??? 48 Thermal event interrupts
THR: ??? 0 Threshold APIC interrupts
MCE: ??? 0 Machine check exceptions
MCP: ??? 3 Machine check polls
ERR: 0
MIS: 0

3r33770.  
The file /proc /interrupts provides a table of the number of interrupts on each of the processors in the following form: 3r37070.  
3r33770.  
3r33737.  
3r3756. First column: interrupt number
 
3r3756. CPUx columns: interrupt counters on each of the
processors.  
3r3756. Next column: interrupt type:
 
3r33737.  
3r3756. IO-APIC-edge - interrupt on the front to the controller I /O APIC
 
3r3756. IO-APIC-fasteoi - level interrupt on I /O controller APIC
 
3r3756. PCI-MSI-edge - MSI interrupt 3r3373767.  
3r3756. XT-PIC-XT-PIC - interrupt on the PIC controller (we will see later)
 
3r3769. 3r33767.  
3r3756. Last column: device associated with this interrupt
 
3r3769. 3r33770.  
So, as it should be in a modern system, they are used for devices and drivers that support MSI /MSI-X interrupts. The remaining interrupts are routed through I /O APIC. 3r33770.  
3r33770.  
Support for an MSI /MSI-X device must be designated as the corresponding Capability in its PCI configuration space. 3r33770.  
3r33770.  
In the confirmation, we give a small fragment of the lspci output for devices for which it is indicated that they use MSI /MSI-X. In our case, these are the SATA controller (ahci interrupt), 2 ethernet controllers (interrupt eth58 * and eth59 *), the graphics controller (i915) and 2 HD Audio controllers (snd_hda_intel). 3r33770.  
3r33770.  
3r3675. lspci -v
3r33770.  
3r3675. 00: 02.0 VGA compatible controller: Intel Corporation Haswell-ULT Integrated Graphics Controller (rev 09) (prog-if 00[VGA controller])
Capabilities:[90]MSI: Enable + Count = 1/1 Maskable- 64bit-
Capabilities:[d0]Power Management version 2
Capabilities:[a4]PCI Advanced Features
Kernel driver in use: i915
00: 03.0 Audio device: Intel Corporation Haswell-ULT HD Audio Controller (rev 09
Capabilities:[60]MSI: Enable + Count = 1/1 Maskable- 64bit-
Capabilities:[70]Express Root Complex Integrated Endpoint, MSI 003r3783 Kernel driver in use: snd_hda_intel
3r3r???: 1b.0 Audio device: Intel Corporation 8 Series HD Audio Controller (rev 04)
Capabilities:[60]MSI: Enable = 1/1 Maskable-64bit +
Capabilities:[70]Express Root Complex Integrated Endpoint, MSI 00
Capabilities:[100]Virtual Channel 3r3783. : Intel Corporation 8 Series SATA Controller 1[AHCI mode](Rev 04) (prog-if 01[AHCI 1.0])
Capabilities:[80]MSI: Enable + Count = 1/1 Maskable- 64bit- 3r3r???. Capabilities:[70]Power Management version 3
Capabilities:[a8]SATA HBA v???r3r3783. Kernel driver in use: ahci
05: 00.0 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
Capabilities:[50]MSI: Enable- Count = 1/1 Maskable + 64bit +
Capabilities:[70]MSI-X: Enable + Count = 10 Masked-
Capabilities:[a0]Express Endpoint, MSI 00
Kernel driver in use: igb
05: 00.1 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
Capabilities:[50]MSI: Enable- Count = 1/1 Maskable + 64bit +
Capabilities:[70]MSI-X: Enable + Count = 10 Masked-
Capabilities:[a0]Express Endpoint, MSI 00
Kernel driver in use: igb
3r33770.  
As we can see, these devices have the line either “MSI: Enable +” or “MSI-X: Enable +”
 
3r33770.  
Let's start to degrade the system. To begin, boot with the option pci = nomsi. 3r33770.  
3r33770.  
3r3694. pci = nomsi
3r33770.  
Thanks to this option, MSI interrupts will become IO-APIC /XT-PIC depending on the used interrupt controller
 
3r33770.  
In this case, we still have an APIC priority interrupt controller, so the picture will be 3r-3770.  
3r33770.  
3r3675. CPU0 CPU1 CPU2 CPU3
0: ??? 0 IO-APIC-edge timer
1: ??? 1 IO-APIC-edge i8042
8: ??? 0 IO-APIC-edge rtc0
9: ??? 0 IO-APIC-fasteoi acpi
12: ??? 1 IO-APIC-edge
16: ??? 555 IO-APIC-fasteoi i91? snd_hda_intel, eth59 3r3r???: ??? 34 IO-APIC-fasteoi eth58
21: ??? 2088 IO-APIC-fasteoi ahci
22: ??? 170 IO-APIC-fasteoi snd_hda_intel
23: ??? 8 IO-APIC-fasteoi ehci_hcd: usb1
NMI: ??? 0 Non-maskable interrupts
LOC: ??? 2617 Local timer interrupts
SPU: ??? 0 Spurious interrupts
PMI: ??? 0 Performance monitoring interrupts
IWI: ??? 85 IRQ work interrupts
RTR: ??? 0 APIC ICR read retries
RES: ??? 1569 Rescheduling interrupts
CAL: ??? 555 Function call interrupts
TLB: ??? 179 TLB shootdowns
TRM: ??? 102 Thermal event interrupts
THR: ??? 0 Threshold APIC interrupts
MCE: ??? 0 Machine check exceptions
MCP: ??? 2 Machine check polls
ERR: 0
MIS: 0
3r33770.  
All MSI /MSI-X interrupts are expected to disappear. Instead, devices now use interrupts of the form IO-APIC-fasteoi. 3r33770.  
3r33770.  
Note that earlier before enabling this option, eth58 and eth59 had 9 interrupts each! And now just one by one. After all, as we remember, without MSI, only one interrupt is available for one PCI function! 3r33770.  
3r33770.  
Some information from dmesg on initializing ethernet controllers:
 
3r33770.  
- boot without option pci = nomsi:
 
3r33770.  
3r3675. igb: Intel (R) Gigabit Ethernet Network Driver - version ???-k
igb: Copyright (c) 2007-2013 Intel Corporation.
acpi: acpi_pci_irq_enable: igb 0000: 05: 00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
igb 0000: 05: 00.0: irq 63 for MSI /MSI-X
igb 0000: 05: 00.0: irq 64 for MSI /MSI-X
igb 0000: 05: 00.0: irq 65 for MSI /MSI-X
igb 0000: 05: 00.0: irq 66 for MSI /MSI-X
igb 0000: 05: 00.0: irq 67 for MSI /MSI-X
igb 0000: 05: 00.0: irq 68 for MSI /MSI-X
igb 0000: 05: 00.0: irq 69 for MSI /MSI-X
igb 0000: 05: 00.0: irq 70 for MSI /MSI-X
igb 0000: 05: 00.0: irq 71 for MSI /MSI-X
igb 0000: 05: 00.0: irq 63 for MSI /MSI-X
igb 0000: 05: 00.0: irq 64 for MSI /MSI-X
igb 0000: 05: 00.0: irq 65 for MSI /MSI-X
igb 0000: 05: 00.0: irq 66 for MSI /MSI-X
igb 0000: 05: 00.0: irq 67 for MSI /MSI-X
igb 0000: 05: 00.0: irq 68 for MSI /MSI-X
igb 0000: 05: 00.0: irq 69 for MSI /MSI-X
igb 0000: 05: 00.0: irq 70 for MSI /MSI-X
igb 0000: 05: 00.0: irq 71 for MSI /MSI-X
igb 0000: 05: 00.0: added PHC on eth0
igb 0000: 05: 00.0: Intel (R) Gigabit Ethernet Network Connection
igb 0000: 05: 00.0: eth0: (PCIe: 5.0Gb /s: Width x1) 00: 15: d5: 03: 00: 2a
igb 0000: 05: 00.0: eth0: PBA No: 106300-000
igb 0000: 05: 00.0: Using MSI-X interrupts. 4 rx queue (s), 4 tx queue (s)
acpi: acpi_pci_irq_enable: igb 0000: 05: 00.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17
igb 0000: 05: 00.1: irq 72 for MSI /MSI-X
igb 0000: 05: 00.1: irq 73 for MSI /MSI-X
igb 0000: 05: 00.1: irq 74 for MSI /MSI-X
igb 0000: 05: 00.1: irq 75 for MSI /MSI-X
igb 0000: 05: 00.1: irq 76 for MSI /MSI-X
igb 0000: 05: 00.1: irq 77 for MSI /MSI-X
igb 0000: 05: 00.1: irq 78 for MSI /MSI-X
igb 0000: 05: 00.1: irq 79 for MSI /MSI-X
igb 0000: 05: 00.1: irq 80 for MSI /MSI-X
igb 0000: 05: 00.1: irq 72 for MSI /MSI-X
igb 0000: 05: 00.1: irq 73 for MSI /MSI-X
igb 0000: 05: 00.1: irq 74 for MSI /MSI-X
igb 0000: 05: 00.1: irq 75 for MSI /MSI-X
igb 0000: 05: 00.1: irq 76 for MSI /MSI-X
igb 0000: 05: 00.1: irq 77 for MSI /MSI-X
igb 0000: 05: 00.1: irq 78 for MSI /MSI-X
igb 0000: 05: 00.1: irq 79 for MSI /MSI-X
igb 0000: 05: 00.1: irq 80 for MSI /MSI-X
igb 0000: 05: 00.1: added PHC on eth1
igb 0000: 05: 00.1: Intel (R) Gigabit Ethernet Network Connection
igb 0000: 05: 00.1: eth1: (PCIe: 5.0Gb /s: Width x1) 00: 15: d5: 03: 00: 2b
igb 0000: 05: 00.1: eth1: PBA No: 106300-000
igb 0000: 05: 00.1: Using MSI-X interrupts. 4 rx queue (s), 4 tx queue (s)
3r33770.  
- boot with option pci = nomsi
 
3r33770.  
3r3675. igb: Intel (R) Gigabit Ethernet Network Driver - version ???-k
igb: Copyright (c) 2007-2013 Intel Corporation.
acpi: acpi_pci_irq_enable: igb 0000: 05: 00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
igb 0000: 05: 00.0: added PHC on eth0
igb 0000: 05: 00.0: Intel (R) Gigabit Ethernet Network Connection
igb 0000: 05: 00.0: eth0: (PCIe: 5.0Gb /s: Width x1) 00: 15: d5: 03: 00: 2a
igb 0000: 05: 00.0: eth0: PBA No: 106300-000
igb 0000: 05: 00.0: Using legacy interrupts. 1 rx queue (s), 1 tx queue (s)
acpi: acpi_pci_irq_enable: igb 0000: 05: 00.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17
igb 0000: 05: 00.1: added PHC on eth1
igb 0000: 05: 00.1: Intel (R) Gigabit Ethernet Network Connection
igb 0000: 05: 00.1: eth1: (PCIe: 5.0Gb /s: Width x1) 00: 15: d5: 03: 00: 2b
igb 0000: 05: 00.1: eth1: PBA No: 106300-000
igb 0000: 05: 00.1: Using legacy interrupts. 1 rx queue (s), 1 tx queue (s)
3r33770.  
Due to the reduction in the number of interrupts per device, enabling this option can lead to a significant limitation of driver performance (this is not taking into account the fact that according to Intel research 3r33379. Interrupt through MSI 3 times faster than through IO-APIC and 5 times faster than through PIC). 3r33770.  
3r33770.  
3r3694. noapic
3r33770.  
This option disables I /O APIC. MSI interrupts can still go to all CPUs, but interrupts from devices can only go to CPU? since the PIC is connected only to CPU0. But LAPIC works and other CPUs can work and handle interrupts. 3r33770.  
3r33770.  
3r3675. CPU0 CPU1 CPU2 CPU3
0: ??? 0 XT-PIC-XT-PIC timer
1: ??? 0 XT-PIC-XT-PIC i8042
2: ??? 0 XT-PIC-XT-PIC cascade
8: ??? 0 XT-PIC-XT-PIC rtc0
9: ??? 0 XT-PIC-XT-PIC acpi
12: ??? 0 XT-PIC-XT-PIC ehci_hcd: usb1
56: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
57: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
58: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
59: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
60: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
61: ??? 0 PCI-MSI-edge aerdrv, PCIe PME
62: ??? 811 PCI-MSI-edge ahci
63: ??? 0 PCI-MSI-edge eth59
64: ??? 3 PCI-MSI-edge eth59-rx-0
65: ??? 178 PCI-MSI-edge eth59-rx-1
66: ??? 2 PCI-MSI-edge eth59-rx-2
67: ??? 1 PCI-MSI-edge eth59-rx-3
68: ??? 10 PCI-MSI-edge eth59-tx-0
69: ??? 23 PCI-MSI-edge eth59-tx-1
70: 1???? PCI-MSI-edge eth59-tx-2
71: ??? 2 PCI-MSI-edge eth59-tx-3
72: ??? 0 PCI-MSI-edge eth58
73: ??? 27 PCI-MSI-edge eth58-rx-0
74: ??? 5 PCI-MSI-edge eth58-rx-1
75: ??? 5 PCI-MSI-edge eth58-rx-2
76: ??? 5 PCI-MSI-edge eth58-rx-3
77: ??? 27 PCI-MSI-edge eth58-tx-0
78: ??? 5 PCI-MSI-edge eth58-tx-1
79: ??? 5 PCI-MSI-edge eth58-tx-2
80: ??? 5 PCI-MSI-edge eth58-tx-3
81: ??? 7 PCI-MSI-edge snd_hda_intel
82: ??? 129 PCI-MSI-edge i915
83: ??? 59 PCI-MSI-edge snd_hda_intel
NMI: ??? 0 Non-maskable interrupts
LOC: ??? 1474 Local timer interrupts
SPU: ??? 0 Spurious interrupts
PMI: ??? 0 Performance monitoring interrupts
IWI: ??? 91 IRQ work interrupts
RTR: ??? 0 APIC ICR read retries
RES: ??? 1541 Rescheduling interrupts
CAL: ??? 567 Function call interrupts
TLB: ??? 137 TLB shootdowns
TRM: ??? 78 Thermal event interrupts
THR: ??? 0 Threshold APIC interrupts
MCE: 0     ??? Machine check exceptions
MCP: ??? 2 Machine check polls
ERR: 0
MIS: 0
3r33770.  
As you can see, all IO-APIC- * interrupts turned into XT-PIC-XT-PIC, and these interrupts are routed only on CPU0. The MSI interrupts remain unchanged and go to all CPU0-3. 3r33770.  
3r33770.  
3r3694. nolapic
3r33770.  
Disables LAPIC. MSI interrupts cannot work without LAPIC, I /O APIC cannot work without LAPIC. Therefore, all interrupts from the devices will go to the PIC, and it only works with CPU0. And without LAPIC, the other CPUs will not even work in the system. 3r33770.  
3r33770.  
3r3675. CPU0 3r3783. 0: 6416 XT-PIC-XT-PIC timer
1: 2 XT-PIC-XT-PIC i8042
2-0 XT-PIC-XT-PIC cascade
3: 5067 XT-PIC-XT-PIC aerdrv, aerdrv, PCIe PME, PCIe PME, i91? snd_hda_intel, eth59
4:32 XT-PIC-XT-PIC aerdrv, aerdrv, PCIe PME, PCIe PME, eth58
5: 0 XT-PIC-XT-PIC aerdrv, PCIe PME
6: 0 XT-PIC-XT-PIC aerdrv, PCIe PME
8: 1 XT-PIC-XT-PIC rtc0
9: 0 XT-PIC-XT-PIC acpi
11: 274 XT-PIC-XT-PIC snd_hda_intel
12: 202 XT-PIC-XT-PIC ehci_hcd: usb1
15: 7903 XT-PIC-XT-PIC ahci
NMI: 0 Non-maskable interrupts
LOC: 0 Local timer interrupts
SPU: 0 Spurious interrupts
PMI: 0 Performance monitoring interrupts
IWI: 0 IRQ work interrupts
RTR: 0 APIC ICR read retries
RES: 0 Rescheduling interrupts
CAL: 0 Function call interrupts
TLB: 0 TLB shootdowns
TRM: 0 Thermal event interrupts
THR: 0 Threshold APIC interrupts
MCE: 0 Machine check exceptions
MCP: 1 Machine check polls
ERR: 0
MIS: 0

3r33770.  
3r3694. Combinations:
3r33770.  
In fact, there is only one for the new version: “noapic pci = nomsi”. All interrupts from devices can only go to CPU0 through the PIC. But LAPIC works and other CPUs can work and handle interrupts. 3r33770.  
3r33770.  
One, because nothing can be combined with “nolapic”, because this option will make I /O APIC and MSI unavailable. So if you once registered the noapic nolapic boot options (or the most common variant is “acpi = off noapic nolapic”), then apparently you typed extra letters. 3r33770.  
3r33770.  
So, the output from “noapic pci = nomsi”:
 
3r33770.  
3r3675. CPU0 CPU1 CPU2 CPU3
0: ??? 0 XT-PIC-XT-PIC timer
1: ??? 0 XT-PIC-XT-PIC i8042
2: ??? 0 XT-PIC-XT-PIC cascade
3: ??? 0 XT-PIC-XT-PIC i91? snd_hda_intel, eth59
4: ??? 0 XT-PIC-XT-PIC eth58
8: ??? 0 XT-PIC-XT-PIC rtc0
9: ??? 0 XT-PIC-XT-PIC acpi
11: ??? 0 XT-PIC-XT-PIC snd_hda_intel
12: ??? 0 XT-PIC-XT-PIC ehci_hcd: usb1
15: ??? 0 XT-PIC-XT-PIC ahci
NMI: ??? 0 Non-maskable interrupts
LOC: ??? 1697 Local timer interrupts
SPU: ??? 0 Spurious interrupts
PMI: ??? 0 Performance monitoring interrupts
IWI: ??? 135 IRQ work interrupts
RTR: ??? 0 APIC ICR read retries
RES: ??? 1833 Rescheduling interrupts
CAL: 43?55?54?558 Function call interrupts
TLB: 12?18?15?274 TLB shootdowns
TRM: ??? 116 Thermal event interrupts
THR: ??? 0 Threshold APIC interrupts
MCE: ??? 0 Machine check exceptions
MCP: ??? 2 Machine check polls
ERR: 0
MIS: 0
3r33770.  
3r3694. Interrupt routing tables and options "acpi = noirq", "pci = noacpi", "acpi = off"
3r33770.  
How does the operating system get information about routing interrupts from devices? The BIOS prepares information for the OS in the form: 3r33770.  
3r33770.  
3r33737.  
3r3756. ACPI tables (_PIC /_PRT methods)
 
3r3756. _MP_ tables (MPtable)
 
3r3756. $ PIR table
 
3r3756. Registers 0x3C /0x3D of the PCI configuration space of devices
 
3r3769. 3r33770.  
It should be noted that to designate MSI interrupts, the BIOS does not need to do anything extra; all the above information is needed only for APIC /PIC interrupt lines. 3r33770.  
3r33770.  
The tables in the list above are indicated in order of priority. Consider this in more detail. 3r33770.  
3r33770.  
Suppose the BIOS has provided all this data and we are loading without any additional options:
 
3r33770.  
3r33737.  
3r3756. The OS finds the ACPI tables
 
3r3756. The OS executes the ACPI "_PIC" method, passing it the argument that it needs to be loaded in APIC mode. Here the method code usually stores the selected mode in a variable (say PICM = 1)
 
3r3756. To get interrupt data, the OS calls the ACPI method "_PRT". He internally checks the PICM variable and returns the routing for the APIC case 3r-3767.  
3r3769. 3r33770.  
In case we are loading with option noapic :
 
3r33770.  
3r33737.  
3r3756. The OS finds the ACPI tables
 
3r3756. The OS executes the ACPI "_PIC" method, passing it the argument that it is necessary to boot in PIC mode. Here the code of the method usually saves the selected mode in a variable (for example, PICM = 0)
 
3r3756. To get interrupt data, the OS calls the ACPI method "_PRT". He internally checks the PICM variable and returns the routing for the PIC case 3r-3767.  
3r3769. 3r33770.  
If the ACPI table is missing or the interrupt routing functionality via ACPI is disabled using options 3r376565. acpi = noirq [/b] or pci = noacpi (or ACPI is completely disabled using acpi = off ), the OS looks for the MPtable (_MP_) table for routing interrupts:
 
3r33770.  
3r33737.  
3r3756. The OS does not find /look at the ACPI tables
 
3r3756. The OS finds the MPtable (_MP_) table
 
3r3769. 3r33770.  
If the ACPI table is missing or the interrupt routing functionality via ACPI is disabled using options 3r376565. acpi = noirq [/b] or pci = noacpi (or ACPI is completely disabled using acpi = off ) and if the MPtable (_MP_) table is missing (or the download option 3r3373765. noapic [/b] or nolapic ) is passed:
 
3r33770.  
3r33737.  
3r3756. The OS does not find /look at the ACPI table
 
3r3756. The OS does not find /look at the MPtable (_MP_) table
 
3r3756. The OS finds the table $ PIR
 
3r3769. 3r33770.  
If there is no $ PIR table, or it is not complete, then the operating system for guessing interrupts will look at the values ​​of the 0x3C /0x3D registers of the configuration space of PCI devices. 3r33770.  
3r33770.  
It should be remembered that not every BIOS provides all 3 tables (ACPI /MPtable /$ PIR), so if you passed the option to the loader to refuse to use ACPI or ACPI and MPtable for routing interrupts, it’s not a fact that your system boots. 3r33770.  
3r33770.  
3r33737. Note [/b] : in general, interrupt routing using ACPI in the case of APIC coincides with interrupt routing via MPtbale. And routing interrupts via ACPI in the case of using the PIC coincides with the routing interrupts through $ PIR. So the findings /proc /interrupts should not be different. However, in the process of research I noticed one oddity. When routing via MPtable in the output for some reason, there is a cascade interrupt "XT-PIC-XT-PIC cascade". 3r33770.  
3r33770.  
3r3675. CPU0 CPU1 CPU2 CPU3
0: ??? 0 IO-APIC-edge timer
1: ??? 0 IO-APIC-edge i8042
2: ??? 0 XT-PIC-XT-PIC cascade
8: ??? 0 IO-APIC-edge rtc0
9: ??? 0 IO-APIC-edge acpi

3r33770.  
It is a bit strange that this happens, but in 3r-3688. the documentation kernel 3r3689. It seems to say that this is normal 3r33770.  
3r33770.  
3r3694. Conclusion: 3r39595. 3r33770.  
In conclusion, we again denote the parsed options. 3r33770.  
3r33770.  
Interrupt Controller Selection Options:
 
3r33770.  
3r33737.  
3r3756. 3r33737. pci = nomsi [/b] - MSI interrupts will become IO-APIC /XT-PIC depending on the used interrupt controller
 
3r3756. 3r33737. noapic [/b] - Disables I /O APIC. MSI interrupts can still go to all CPUs, other interrupts from devices can only go to the PIC, and it only works with CPU0. But LAPIC works and other CPUs can work and process interrupts
 
3r3756. 3r33737. noapic pci = nomsi [/b] - All interrupts from devices can only go to the PIC, and it only works with CPU0. But LAPIC works and other CPUs can work and process interrupts
 
3r3756. 3r33737. nolapic [/b] - Disables LAPIC. MSI interrupts cannot work without LAPIC, I /O APIC cannot work without LAPIC. All interrupts from the devices will go to the PIC, and it only works with CPU0. And without LAPIC, the rest of the CPU will not work. 3r33767.  
3r3769. 3r33770.  
Options for selecting the interrupt routing priority table: 3r37070.  
3r33770.  
3r33737.  
3r3756. 3r33737. without options [/b] - routing through APIC using ACPI tables
 
3r3756. 3r33737. noapic [/b] - routing through PIC using the ACPI tables
 
3r3756. 3r33737. acpi = noirq [/b] ( Pci = noacpi / Acpi = off ) - routing through APIC using the MPtable table
 
3r3756. 3r33737. acpi = noirq [/b] ( Pci = noacpi / Acpi = off ) noapic ( Nolapic ) - routing through the PIC using the $ PIR table
 
3r3769. 3r33770.  
In the next part, let's see how the coreboot configures the chipset for routing interrupts.
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